- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379008 > CY3687 (Cypress Semiconductor Corp.) MoBL-USB⑩ FX2LP18 USB Microcontroller PDF資料下載
參數(shù)資料
| 型號： | CY3687 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | MoBL-USB⑩ FX2LP18 USB Microcontroller |
| 中文描述： | 的MoBL - USB FX2LP18的USB微控制器⑩ |
| 文件頁數(shù)： | 14/39頁 |
| 文件大?。?/td> | 453K |
| 代理商： | CY3687 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
CY7C68053
Document # 001-06120 Rev *H
Page 14 of 39
PORT D
8A
PD0 or
FD[8]
I/O/Z
I
(PD0)
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[8]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[9]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[10]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[11]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[12]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[13]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[14]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[15]
is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
RDY0
is a GPIF input signal.
SLRD
is the input only read strobe with programmable polarity (FIFOPIN-
POLAR.3) for the slave FIFOs connected to FD[7:0] or FD[15:0].
Multiplexed pin whose function is selected by IFCONFIG[1:0].
RDY1
is a GPIF input signal.
SLWR
is the input only write strobe with programmable polarity (FIFOPIN-
POLAR.2) for the slave FIFOs connected to FD[7:0] or FD[15:0].
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL0
is a GPIF control output.
FLAGA
is a programmable slave FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins.
Multiplexed pin whose function is selected by IFCONFIG[1:0].
CTL1
is a GPIF control output.
FLAGB
is a programmable slave FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
Multiplexed pin whose function is selected IFCONFIG[1:0].
CTL2
is a GPIF control output.
FLAGC
is a programmable slave FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
Interface Clock, used for synchronously clocking data into or out of the slave
FIFOs. IFCLK also serves as a timing reference for all slave FIFO control
signals and GPIF. When internal clocking is used (IFCONFIG.7 = 1) the IFCLK
pin can be configured to output 30 or 48 MHz by bits IFCONFIG.5 and
IFCONFIG.6. IFCLK may be inverted, whether internally or externally sourced,
by setting the bit IFCONFIG.4 =1.
7A
PD1 or
FD[9]
I/O/Z
I
(PD1)
6B
PD2 or
FD[10]
I/O/Z
I
(PD2)
6A
PD3 or
FD[11]
I/O/Z
I
(PD3)
3B
PD4 or
FD[12]
I/O/Z
I
(PD4)
3A
PD5 or
FD[13]
I/O/Z
I
(PD5)
3C
PD6 or
FD[14]
I/O/Z
I
(PD6)
2A
PD7 or
FD[15]
I/O/Z
I
(PD7)
1A
RDY0 or
SLRD
Input
N/A
1B
RDY1 or
SLWR
Input
N/A
7H
CTL0 or
FLAGA
O/Z
H
7G
CTL1 or
FLAGB
O/Z
H
8H
CTL2 or
FLAGC
O/Z
H
2G
IFCLK
I/O/Z
Z
Table 7. FX2LP18 Pin Descriptions
(continued)
[9]
56 VFBGA
Name
Type
Default
Description
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY37128VP160-100BAXC | 5V, 3.3V, ISRTM High-Performance CPLDs |
| CY37032P44-125AC | 5V, 3.3V, ISRTM High-Performance CPLDs |
| CY37064P44-200AC | 5V, 3.3V, ISR⑩ High-Performance CPLDs |
| CY37064P44-200JC | 5V, 3.3V, ISR⑩ High-Performance CPLDs |
| CY37384VP100-200JXC | 5V, 3.3V, ISRTM High-Performance CPLDs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY3688 | 功能描述:界面開發(fā)工具 CY3688 RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CY3690 | 功能描述:開發(fā)板和工具包 - 其他處理器 USB 2.0 DVEL KIT RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| CY3691 | 功能描述:開發(fā)板和工具包 - 其他處理器 USB 2.0 DVEL KIT RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| CY3692 | 功能描述:時鐘和定時器開發(fā)工具 Socket adapter "for CY23FP12" RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| CY3693 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PTG Programming Kit |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。