參數(shù)資料
型號： CY3687
廠商： Cypress Semiconductor Corp.
英文描述： MoBL-USB⑩ FX2LP18 USB Microcontroller
中文描述： 的MoBL - USB FX2LP18的USB微控制器⑩
文件頁數(shù)： 16/39頁
文件大?。?/td> 453K
代理商： CY3687
CY7C68053
Document # 001-06120 Rev *H
Page 16 of 39
5. Register Summary
FX2LP18 register bit definitions are described in the
MoBL-USB FX2LP18 TRM
in greater detail.
Table 8. FX2LP18 Register Summary
Hex
Size Name
GPIF Waveform Memories
128 WAVEDATA
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
E400
GPIF Waveform
descriptor 0, 1, 2, 3 data
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
E480
128 Reserved
GENERAL CONFIGURATION
GPCR2
E50D
General Purpose Configura-
tion Register 2
CPU Control and Status
Interface Configuration
(Ports, GPIF, Slave FIFOs)
Slave FIFO FLAGA and
FLAGB pin configuration
Slave FIFO FLAGC and
FLAGD pin configuration
Restore FIFOs to default
state
Breakpoint control
Breakpoint address H
Breakpoint address L
Reserved
Slave FIFO interface pins
polarity
Chip revision
Reserved
Reserved
Reserved
FULL_SPEED
_ONLY
CLKSPD1
IFCLKPOL
Reserved
Reserved
Reserved
Reserved
00000000 R
E600
E601
1
1
CPUCS
IFCONFIG
0
0
PORTCSTB
IFCLKOE
CLKSPD0
ASYNC
CLKINV
GSTATE
CLKOE
IFCFG1
8051RES
IFCFG0
00000010 rrbbbbbr
10000000 RW
IFCLKSRC
3048MHZ
E602
1
PINFLAGSAB
[10]
PINFLAGSCD
[10]
FLAGB3
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0
00000000 RW
E603
1
FLAGD3
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
00000000 RW
E604
1
FIFORESET
[10]
BREAKPT
BPADDRH
BPADDRL
Reserved
FIFOPINPOLAR
[10]
REVID
NAKALL
0
0
0
EP3
EP2
EP1
EP0
xxxxxxxx W
E605
E606
E607
E608
E609
1
1
1
1
1
0
0
0
0
BREAK
A11
A3
0
SLRD
BPPULSE
A10
A2
0
SLWR
BPEN
A9
A1
0
EF
0
00000000 rrrrbbbr
xxxxxxxx RW
xxxxxxxx RW
00000000 rrrrrrbb
00000000 rrbbbbbb
A15
A7
0
0
A14
A6
0
0
A13
A5
0
A12
A4
0
SLOE
A8
A0
0
FF
PKTEND
E60A
1
rv7
rv6
rv5
rv4
rv3
rv2
rv1
rv0
RevA
00000001
00000000 rrrrrrbb
R
E60B
1
REVCTL
[10]
UDMA
GPIFHOLDAMOUNT MSTB hold time
Chip revision control
0
0
0
0
0
0
dyn_out
enh_pkt
E60C
1
(for UDMA)
0
0
0
0
0
0
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
3
Reserved
ENDPOINT CONFIGURATION
EP1OUTCFG
E610
1
Endpoint 1-OUT
configuration
Endpoint 1-IN
configuration
Endpoint 2 configuration
Endpoint 4 configuration
Endpoint 6 configuration
Endpoint 8 configuration
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
E611
1
EP1INCFG
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
E612
E613
E614
E615
1
1
1
1
2
1
EP2CFG
EP4CFG
EP6CFG
EP8CFG
Reserved
EP2FIFOCFG
[10]
EP4FIFOCFG
[10]
EP6FIFOCFG
[10]
EP8FIFOCFG
[10]
Reserved
EP2AUTOINLENH
[10
Endpoint 2 AUTOIN
VALID
VALID
VALID
VALID
DIR
DIR
DIR
DIR
TYPE1
TYPE1
TYPE1
TYPE1
TYPE0
TYPE0
TYPE0
TYPE0
SIZE
0
SIZE
0
0
0
0
0
BUF1
0
BUF1
0
BUF0
0
BUF0
0
10100010 bbbbbrbb
10100000 bbbbrrrr
11100010 bbbbbrbb
11100000 bbbbrrrr
E618
Endpoint 2/Slave FIFO
configuration
Endpoint 4/Slave FIFO
configuration
Endpoint 6/Slave FIFO
configuration
Endpoint 8/Slave FIFO
configuration
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
E619
1
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
E61A
1
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
E61B
1
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
E61C
E620
4
1
packet length H
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
E621
1
EP2AUTOINLENL
[10]
Endpoint 2 AUTOIN
packet length L
Endpoint 4 AUTOIN
packet length H
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E622
1
EP4AUTOINLENH
[10
]
0
0
0
0
0
0
PL9
PL8
00000010 rrrrrrbb
E623
1
EP4AUTOINLENL
[10]
Endpoint 4 AUTOIN
packet length L
Endpoint 6 AUTOIN
packet length H
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E624
1
EP6AUTOINLENH
[10
]
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
E625
1
EP6AUTOINLENL
[10]
Endpoint 6 AUTOIN
packet length L
Endpoint 8 AUTOIN
packet length H
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E626
1
EP8AUTOINLENH
[10
]
0
0
0
0
0
0
PL9
PL8
00000010 rrrrrrbb
E627
1
EP8AUTOINLENL
[10]
Endpoint 8 AUTOIN
packet length L
ECC Configuration
ECC Reset
ECC1 Byte 0 address
ECC1 Byte 1 address
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E628
E629
E62A
E62B
1
1
1
1
ECCCFG
ECCRESET
ECC1B0
ECC1B1
0
x
0
x
0
x
0
x
0
x
0
x
0
x
ECCM
x
LINE8
LINE0
00000000 rrrrrrrb
00000000 W
00000000 R
00000000 R
LINE15
LINE7
LINE14
LINE6
LINE13
LINE5
LINE12
LINE4
LINE11
LINE3
LINE10
LINE2
LINE9
LINE1
Note
10.Read and writes to these registers may require synchronization delay, see
MoBL-USB FX2LP18 Technical Reference Manual
for ‘Synchronization Delay.’
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