參數(shù)資料
型號： CY3687
廠商： Cypress Semiconductor Corp.
英文描述： MoBL-USB⑩ FX2LP18 USB Microcontroller
中文描述： 的MoBL - USB FX2LP18的USB微控制器⑩
文件頁數(shù)： 30/39頁
文件大?。?/td> 453K
代理商： CY3687
CY7C68053
Document # 001-06120 Rev *H
Page 30 of 39
There is no specific timing requirement that needs to be met for
asserting the PKTEND pin with regards to asserting SLWR.
PKTEND can be asserted with the last data value clocked into
the FIFOs or thereafter. The only consideration is that the setup
time t
SPE
and the hold time t
PEH
must be met.
Although there are no specific timing requirements for the
PKTEND assertion, there is a specific corner case condition that
needs attention while using the PKTEND to commit a one
byte/word packet. There is an additional timing requirement that
needs to be met when the FIFO is configured to operate in auto
mode and you want to send two packets back to back: a full
packet (full defined as the number of bytes in the FIFO meeting
the level set in AUTOINLEN register) committed automatically
followed by a short one byte/word packet committed manually
using the PKTEND pin. In this particular scenario, the user must
make sure to assert PKTEND at least one clock cycle after the
rising edge that caused the last byte/word to be clocked into the
previous auto committed packet.
Figure 14
shows this scenario.
X is the value the AUTOINLEN register is set to when the IN
endpoint is configured to be in auto mode.
Figure 14
shows a scenario where two packets are being
committed. The first packet is committed automatically when the
number of bytes in the FIFO reaches X (value set in AUTOINLEN
register) and the second one byte/word short packet is
committed manually using PKTEND. Note that there is at least
one IFCLK cycle timing between the assertion of PKTEND and
clocking of the last byte of the previous packet (causing the
packet to be committed automatically). Failing to adhere to this
timing, results in the FX2LP18 failing to send the one byte/word
short packet.
9.8 Slave FIFO Asynchronous Packet End Strobe
Table 20.Slave FIFO Asynchronous Packet End Strobe Parameters
[20]
Parameter
t
PEpwl
t
PWpwh
t
XFLG
Description
Min.
50
50
Max.
Unit
ns
ns
ns
PKTEND pulse width LOW
PKTEND pulse width HIGH
PKTEND to FLAGS output propagation delay
115
IFCLK
SLWR
DATA
Figure 14. Slave FIFO Synchronous Write Sequence and Timing Diagram
[17]
t
IFCLK
>= t
SWR
>= t
WRH
X-2
PKTEND
X-3
t
FAH
t
SPE
t
PEH
FIFOADR
t
SFD
t
SFD
t
SFD
X-4
t
FDH
t
FDH
t
FDH
t
SFA
1
X
t
SFD
t
SFD
t
SFD
X-1
t
FDH
t
FDH
t
FDH
At least one IFCLK cycle
FLAGS
t
XFLG
PKTEND
t
PEpwl
t
PEpwh
Figure 15. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
[17]
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CY3688 功能描述:界面開發(fā)工具 CY3688 RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
CY3690 功能描述:開發(fā)板和工具包 - 其他處理器 USB 2.0 DVEL KIT RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
CY3691 功能描述:開發(fā)板和工具包 - 其他處理器 USB 2.0 DVEL KIT RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
CY3692 功能描述:時鐘和定時器開發(fā)工具 Socket adapter "for CY23FP12" RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
CY3693 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:PTG Programming Kit
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