參數(shù)資料
型號: CY3687
廠商: Cypress Semiconductor Corp.
英文描述: MoBL-USB⑩ FX2LP18 USB Microcontroller
中文描述: 的MoBL - USB FX2LP18的USB微控制器⑩
文件頁數(shù): 1/39頁
文件大?。?/td> 453K
代理商: CY3687
CY7C68053
MoBL-USB FX2LP18 USB
Microcontroller
Cypress Semiconductor Corporation
Document # 001-06120 Rev *H
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 6, 2007
1. CY7C68053 Features
USB 2.0 – USB-IF High-Speed and Full-Speed Compliant
(TID# 40000188)
Single-chip integrated USB 2.0 transceiver, smart SIE, and
enhanced 8051 microprocessor
Ideal for mobile applications (cell phone, smart phones,
PDAs, MP3 players)
Ultra low power
Suspend current: 20 μA (typical)
Software: 8051 code runs from:
Internal RAM, which is loaded from EEPROM
16 kBytes of on-chip Code/Data RAM
Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
Buffering options: double, triple, and quad
Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
8- or 16-bit external data interface
Smart Media Standard ECC generation
GPIF (General Programmable Interface)
Allows direct connection to most parallel interface
Programmable waveform descriptors and configuration reg-
isters to define waveforms
Supports multiple Ready and Control outputs
Integrated, industry standard enhanced 8051
48 MHz, 24 MHz, or 12 MHz CPU operation
Four clocks per instruction cycle
Three counter/timers
Expanded interrupt system
Two data pointers
1.8V Core operation
1.8V - 3.3V IO operation
Vectored USB interrupts and GPIF/FIFO interrupts
Separate data buffers for the Setup and Data portions of a
CONTROL transfer
Integrated I
2
C controller, runs at 100 or 400 kHz
Four integrated FIFOs
Integrated glue logic and FIFOs lower system cost
Automatic conversion to and from 16-bit buses
Master or slave operation
Uses external clock or asynchronous strobes
Easy interface to ASIC and DSP ICs
Available in Industrial temperature grade
Available in one Pb-free package with up to 24 GPIOs
56-pin VFBGA (24 GPIOs)
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
Four Clocks/Cycle
I
2
C
Master
VCC
1.5K
D+
D–
A
GPIF
CY
Smart
USB
1.1/2.0
Engine
USB
2.0
XCVR
16 KB
RAM
4 KB
FIFO
Integrated
Full- and High-Speed
XCVR
Additional IOs (24)
CTL (3)
24 MHz
Ext. XTAL
Enhanced USB Core
Simplifies 8051 Code
“Soft Configuration”
Easy Firmware Changes
FIFO and Endpoint Memory
(Master or Slave Operation)
General
Programmable I/F
To Baseband Processors/
Application Processors/
ASICS/DSPs
Abundant IO
High-performance microprocessor
using standard tools
with lower-power options
Connected for
Full-Speed
ECC
MoBL-USB FX2LP18
8/16
Up to 96 MBytes/sec
Burst Rate
Block Diagram
[+] Feedback
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