參數(shù)資料
型號(hào)： C9837AT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： TSSOP-48
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 316K
代理商： C9837AT
+/+
…when timing is critical
C9837
Low EMI Clock Generator for Intel
Mobile 133MHz/2 SO-DIMM Chipset Systems
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
Rev 1.0
3/30/2000
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 15 of 20
http://www.imicorp.com
133MHz Host
100MHz Host
66MHz Host
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
TPeriod
REF period
5,6
69.8413
71.0
69.8413
71.0
69.8413
71.0
ns
Tr / Tf
REF rise and fall times
7
1.0
4.0
1.0
4.0
1.0
4.0
ns
TCCJ
REF Cycle to Cycle Jitter
6
-
1000
-
1000
-
1000
ps
tpZL, tpZH
Output enable delay (all outputs)
8
1.0
10.0
1.0
10.0
1.0
10.0
ns
tpLZ, tpHZ
Output disable delay (all outputs)
13
1.0
10.0
1.0
10.0
1.0
10.0
ns
tstable
All clock Stabilization from power-up
12
33
3
ms
Tduty
Duty Cycle for All outputs
14
45
55
45
55
45
55
%
Note 5: This parameter is measured as an average over 1us duration, with a crystal center frequency of 14.31818MHz
Note 6: All outputs loaded as per Table 6 below. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at
1.25V for 2.5V signals (figures 8a and 8b).
Note 7: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V
and 2.0V for 2.5V signals (see Figures 8a and 8b)
Note 8: Measured from when both SEL1 and SEL0 are switched to high (enable).
Note 9: This measurement is applicable with Spread ON or Spread OFF.
Note 10:Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals, (see
Figures 8a and 8b)
Note 11:Probes are placed on the pins, and measurements are acquired at 0.4V.
Note 12:The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency
output is stable and operating within the specifications
Note 13:Measured from when both SEL1 and SEL0 are switched to low (disable).
Note 14: Device designed for Typical Duty Cycle of 50%.
Clock Name
Max Load (in pF)
CPU(0,1), REF, 48M0(USB)
20
PCI(_F, 1:6), SDRAM(0:3), DCLK, 3V66(0:2)
30
48M_DOT
15
Table 6.
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