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參數(shù)資料
| 型號： | C9837AT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 316K |
| 代理商： | C9837AT |
+/+
…when timing is critical
C9837
Low EMI Clock Generator for Intel
Mobile 133MHz/2 SO-DIMM Chipset Systems
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
Rev 1.0
3/30/2000
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 8 of 20
http://www.imicorp.com
Group Timing Relationships and Tolerances
CPU = 66.6MHz, SDRAM = 100MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
2.5
500
CPU to 3V66
7.5
500
180 degrees phase shift
SDRAM/DCLK to 3V66
0
500
When rising edges line-up
3V66 to PCI
1.5-3.5
500
3V66 leads
PCI to IOAPIC
0
1000
48M(0,1)
Async
N/A
CPU = 100MHz, SDRAM = 100MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
5
500
180 degrees phase shift
CPU to 3V66
5
500
CPU leads
SDRAM/DCLK to 3V66
0
500
When rising edges line-up
3V66 to PCI
1.5-3.5
500
3V66 leads
PCI to IOAPIC
0
1000
48M(0,1)
Async
N/A
CPU = 133.3MHz, SDRAM = 100MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
0
500
When rising edges line-up
CPU to 3V66
0
500
SDRAM/DCLK to 3V66
0
500
When rising edges line-up
3V66 to PCI
1.5-3.5
500
3V66 leads
PCI to IOAPIC
0
1000
48M(0,1)
Async
N/A
CPU = 133.3MHz, SDRAM = 133.3MHz
Offset (ns)
Tolerance (ps)
Conditions
CPU to SDRAM/DCLK
3.75
500
180 degrees phase shift
CPU to 3V66
0
500
SDRAM/DCLK to 3V66
3.75
500
3V66 to PCI
1.5-3.5
500
3V66 leads
PCI to IOAPIC
0
1000
48M(0,1)
Async
N/A
Table 4
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