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參數(shù)資料
| 型號(hào)： | C9837AT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 316K |
| 代理商： | C9837AT |
+/+
…when timing is critical
C9837
Low EMI Clock Generator for Intel
Mobile 133MHz/2 SO-DIMM Chipset Systems
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
Rev 1.0
3/30/2000
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 9 of 20
http://www.imicorp.com
2-Wire I
2C Control Interface
The 2-wire control interface implements a read/write slave only interface according to Philips IC specification. (See
Figure 5 below). The device can be read back by using standard I
2C command bytes. Sub addressing is not supported,
thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows
each clock output to be individually enabled or disabled. 100 Kbits/s (standard mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is an 8-bit address. The LSB address Byte = 0 in write mode.
The device will respond to transfers of 10 bytes (max) of data. The device will generate an acknowledge (low) signal on
SDATA following reception of each byte. Data is transferred MSB first at a max rate of 100kbits/s. This device will also
respond to a D3 address which sets it in a read mode. It will not respond to any other control interface conditions, and
previously set control registers are retained.
When a clock driver is placed in power down mode, the I
2C signals SDATA and SCLK must be tri-stated. In power down,
the device retains all I
2C programming information.
START CONDITION
Transmit
Receive
STOP CONDITION
START CONDITION
Transmit
Receiv
STOP CONDITION
1
8
ACK
MSB
00
0
SDATA
0
1
LSB
COMMAND BYTE
1
SCLK
1
BYTE N
88
8
BYTE 0
BYTE COUNT
ACK
(Don't Care)
(Valid)
Figure 5a (WRITE Cycle)
(Valid)
SDATA
1
0
(Valid)
0
11
8
BYTE N
(Valid)
BYTE COUNT
SCLK
LSB
ACK
8
ACK
8
0
BYTE1
1
ACK
MSB
8
1
(Valid)
BYTE 0
Figure 5b (READ Cycle)
Figure 5. I
2C Communications Waveforms
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