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參數(shù)資料
| 型號： | C9837AT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 316K |
| 代理商： | C9837AT |
+/+
…when timing is critical
C9837
Low EMI Clock Generator for Intel
Mobile 133MHz/2 SO-DIMM Chipset Systems
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
Rev 1.0
3/30/2000
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 4 of 20
http://www.imicorp.com
Power Management Timing
Figure 1
Power Management Current
CONDITIONS
Maximum 2.5 Volt Current
Consumption (VDDC = VDDI =
2.625V)
Maximum 3.3 Volt Current Consumption
(VDD = AVDD = VDDS = 3.465V)
Power down (PD# = LOW)
< 1mA
CPU=66MHz @ max loads
60mA (Preliminary)
160mA (Preliminary)
CPU=100MHz @ max loads
75mA (Preliminary)
160mA (Preliminary)
CPU=133MHz @ max loads
90mA (Preliminary)
160mA (Preliminary)
Table 3
When exiting the power down mode, the application must supply power to the VDD pins a minimum of 200ms before
releasing the PD# pin high to insure that an orderly startup will occur and that the initial clocks that the device produces
are full and correctly compliant with data sheet specified phase relationships.
0ns
10ns
20ns
30ns
40ns
50ns
60ns
CPU 100 MHz
3V66 66 MHz
PCI 33 MHz
IOAPIC 33 MHz
PD#
SDRAM 100 MHz
REF 14.3 MHz
48M (0,1)
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