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參數(shù)資料
| 型號： | C9837AT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 316K |
| 代理商： | C9837AT |
+/+
…when timing is critical
C9837
Low EMI Clock Generator for Intel
Mobile 133MHz/2 SO-DIMM Chipset Systems
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
Rev 1.0
3/30/2000
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 5 of 20
http://www.imicorp.com
CPU_STP# Timing
CPU_STP# is an input to the clock generator. CPU_STP# is asserted asynchronously by the external clock control logic
and is internally synchronized to the external PCI_F output. All other clocks will continue to run while the CPU0 clock is
disabled. The CPU0 is always stopped in a low state and started in such a manner as to guarantee that the high pulse
width is a full pulse. Only one rising edge of PCI_F occurs after the clock control logic is switched for the CPU0 output to
become enabled/disabled.
CPU_STP# Timing Diagram
CPU1
PCI_F
CPU_STP#
CPU0
PCI_STP#
(High)
PD#
Tsu
(High)
Figure 2
Notes:
1.
All internal timing is referenced to the CPU Clock.
2.
CPU_STP# signal is an input signal that is made synchronous to free running PCI_F.
3.
Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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