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參數(shù)資料
| 型號： | C9837AT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 316K |
| 代理商： | C9837AT |
+/+
…when timing is critical
C9837
Low EMI Clock Generator for Intel
Mobile 133MHz/2 SO-DIMM Chipset Systems
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
Rev 1.0
3/30/2000
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 10 of 20
http://www.imicorp.com
Serial Control Registers
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2)
described below will be valid and acknowledged.
Byte 0: CPU Clock Register (1=Enable, 0=Disable)
Bit
@Pup
Pin#
Description
7
1
-
Reserved. Don’t Care
6
1
-
Reserved. Don’t Care
5
1
41
CPU1
4
1
43
CPU0
3
0
-
Spread spectrum (1 = enabled)
2
1
24
48M1(DOT)
1
23
48M0(USB)
0
-
Reserved. Set to 0
Byte 2: 3V66 Clock Register (1=Enable, 0=Disable)
Bit
@Pup
Pin#
Description
7
1
8
3V66_2 (AGP)
6
1
7
3V66_1
5
1
6
3V66_0
4
0
-
Reserved. Set to 0
3
0
-
Reserved. Set to 0
2
0
-
Reserved. Set to 0
1
0
-
Reserved. Set to 0
0
-
Reserved. Set to 0
Byte 4: Reserved Register (1=Enable, 0=Disable)
Bit
@Pup
Pin#
Description
7
0
-
Reserved. Set to 0
6
0
-
Reserved. Set to 0
5
0
-
Reserved. Set to 0
4
0
-
Reserved. Set to 0
3
0
-
Reserved. Set to 0
2
0
-
Reserved. Set to 0
1
0
-
Reserved. Set to 0
0
-
Reserved. Set to 0
Byte 1: SDRAM Clock Register (1=Enable, 0=Disable)
Bit
@Pup
Pin#
Description
7
0
-
Reserved. Set to 0
6
0
-
Reserved. Set to 0
5
1
-
Reserved. Don’t care
4
1
-
Reserved. Don’t care
3
1
34
SDRAM3
2
1
35
SDRAM2
1
37
SDRAM1
0
1
38
SDRAM0
Byte 3: PCI Register (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
Description
7
0
-
Reserved. Set to 0
61
19
PCI6
51
18
PCI5
41
17
PCI4
31
15
PCI3
21
14
PCI2
11
12
PCI1
0
-
SDRAM 133MHz Mode Enable.
Default is disabled = ‘0’, enabled = ‘1’
Byte 5: SSCG Control Register (1 = Enable, 0 = Disable)
Bit
@Pup
Pin#
Description
7
0
-
Spread Mode (0=down, 1=center)
6
0
-
Selects spread bandwidth. See Table 5
5
0
-
Selects spread bandwidth. See Table 5
4
0
-
Reserved. Set to 0
3
0
-
Reserved. Set to 0
2
0
-
Reserved. Set to 0
1
0
-
ESEL1 Expanded Freq. Selection MSB,
See Table 2
0
-
ESEL0 Expanded Freq. Selection LSB,
See Table 2
Note: The Pin# column lists the relevant pin number where applicable. The @Pup column gives the default state at
power up.
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