參數(shù)資料
型號(hào)： C9837AT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： TSSOP-48
文件頁(yè)數(shù)： 12/20頁(yè)
文件大小： 316K
代理商： C9837AT
+/+
…when timing is critical
C9837
Low EMI Clock Generator for Intel
Mobile 133MHz/2 SO-DIMM Chipset Systems
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
Rev 1.0
3/30/2000
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 2 of 20
http://www.imicorp.com
Pin Description
PIN
NAME
PWR
TYPE
DESCRIPTION
48
SEL0/REF
VDD
PU
Power-on Bi-directional Input / Output. At power-up, SEL0 is the input. When
the power supply voltage crosses the input threshold voltage, REF becomes the
output. See frequency Table for SEL0 selections.
2
XIN
Oscillator buffer input. Connect to a crystal or to an external clock.
3
XOUT
Oscillator buffer output. Connect to a crystal. Do not connect when an external
clock is applied at XIN.
41, 43
CPU(1,0)
VDDC
2.5V Host bus clock outputs
6, 7, 8
3V66(0:2)
VDD
3.3V Fixed 66.6MHz clock outputs
11
SEL1/PCI_F
VDDP
PU
Power-on Bi-directional Input / Output. At power-up, SEL1 is the input. When
the power supply voltage crosses the input threshold voltage, PCI_F becomes a
free running PCI clock. This clock continues to run when PCI_STP# is at a logic
low level. See frequency Table for SEL1 selections.
12, 14, 15, 17,
18, 19
PCI (1:6)
VDDP
3.3V PCI clock outputs. These clocks synchronously stop in a low state when
PCI_STP# is brought to a logic low level. They synchronously resume running
when PCI_STP# is brought to a logic high state.
23, 24
48M(0,1)
VDD
3.3V Fixed 48MHz clock outputs
30
CPU_STP#
CPU0 stop clock control input. When this signal is at a logic low level (0), CPU0
clock stops at a logic low level. Using this pin to start and stop CPU0 clock
insures synchronous (no short or long clocks) transitioning of this clock.
10
PCI_STP#
PCI stop clock control input. When this signal is at a logic low level (0), all PCI
clocks (except PCI_F) stop at a logic low level. Using this pin to start and stop
PCI clocks insures synchronous (no short or long clocks) transitioning of these
clocks. This pin has no effect on the PCI_F clock.
26
SDATA
Serial data input pin. Conforms to the Philips I
2C specification of a Slave
Receive/Transmit device. This pin is an input when receiving data. It is an open
drain output when acknowledging or transmitting data. See I
2C function
description.
27
SCLK
Serial clock input pin. Conforms to the Philips I
2C specification. See I2C
function description.
28
PD#
PU
3.3V LVTTL compatible input. When held LOW, the device enters a power down
mode. This pin has an Internal Pull-Up. See power management function.
29
TEST#
3.3V LVTTL compatible input for selecting test mode. See Table 1.
32
DCLK
VDDS
3.3V SDRAM feedback clock output. See Table1 for frequency selection. See
figure 4 for timing relationship.
34, 35, 37, 38
SDRAM(3:0)
VDDS
3.3V SDRAM clock outputs
45, 46
IOAPIC(1,0)
VDDI
2.5V IOAPIC clock outputs. See figure 4 for timing relationships.
42
VDDC
2.5V Power for CPU clock output buffers
31, 36
VDDS
3.3V Power for SDRAM and DCLK clock output buffers
16
VDDP
3.3V Power for PCI clock output buffers
44
VDDI
2.5V Power for IOAPIC clock output buffers
20
AVDD
3.3V Analog Power Supply
1, 9, 25
VDD
3.3V Common Power Supply
4, 5, 13, 21, 22,
33, 39, 40, 47
VSS
Common Ground pins.
A bypass capacitor (0.1
F) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
PU = Internal Pull-Up. Typically 350k (range 200k to 500k).
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