參數(shù)資料
型號(hào): C9837AT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: TSSOP-48
文件頁(yè)數(shù): 14/20頁(yè)
文件大?。?/td> 316K
代理商: C9837AT
+/+
…when timing is critical
C9837
Low EMI Clock Generator for Intel
Mobile 133MHz/2 SO-DIMM Chipset Systems
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
Rev 1.0
3/30/2000
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 3 of 20
http://www.imicorp.com
Expanded Frequency Selection (MHz)
1,2
TEST
#
ESEL
1
ESEL
10
SEL
1
SEL
0
CPU
(0,1)
SDRAM
(0:3), DCLK
3V66
(0:2)
PCI_F,
PCI(1:6)
Notes
0
66.7
100*
66.6
33
0
1
100
100*
66.6
33
0
1
0
133.3
66.6
33
0
1
133.3
100*
66.6
33
0% extension
(Default)
0
1
0
70
105*
70
35
0
1
0
1
105
105*
70
35
0
1
0
140
70
35
0
1
140
105*
70
35
5% extension
1
0
73.3
110*
73.3
36.6
1
0
1
110
110*
73.3
36.6
1
0
1
0
146.7
73.3
36.6
1
0
1
146.7
110*
73.3
36.6
10% extension
1
0
80
120*
80
40
1
0
1
120
120*
80
40
1
0
160
80
40
1
160
120*
80
40
20% extension
Note 1: Extended frequencies are only available via I
2C interface. They are accessable via I2C Byte 5 bits 0,1.
Note 2: 48M_DOT clock is constant at 48MHz and REF is constant at 14.31818MHz for all table selections.
* Will be set to 133MHz and boosted accordingly, when Byte 3 Bit0 is set to logic 1.
Table 2
Power Management Functions
Power Management on this device is controlled by the PD#, CPU_STP# and PCI_STP# pins.
When PD# is high
(default) the device is in normal running mode and all signals are active.
The PD# signal is used to bring all clocks to a low level in an orderly fashion prior to power (all except AVDD) being
removed from the part. When PD# is asserted (forced) low, the device transitions to a shutdown (power down) mode
and all power supplies (3.3V and 2.5V except for AVDD) may then be removed. When PD# is sampled low by two
consecutive rising edges of CPU clock, then all affected clocks are stopped in a low state on their next high-to-low
transition. The REF and USB clocks are stopped in a low state as soon as possible. When in power down (and before
power is removed), all outputs are synchronously stopped in a low state (see Figure 1 below), all PLL’s are shut off, and
the crystal oscillator is disabled. When the device is shutdown, the IC function is also disabled.
At power up, using the PD# select pin, all clocks are started in such a manner as to guarantee a glitch free operation, no
partial clock pulses.
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