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| 型號(hào)： | AMDOPTERON |
| 英文描述： | AMD Opteron - AMD Opteron Processor Data Sheet |
| 中文描述： | AMD Opteron處理器- AMD Opteron處理器的數(shù)據(jù)資料 |
| 文件頁數(shù)： | 76/81頁 |
| 文件大小： | 1189K |
| 代理商： | AMDOPTERON |
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76
Electrical Data
Chapter 7
AMD Opteron
Processor Data Sheet
23932 Rev 3.00 April 2003
Figure 12.Sequencing Relationships for Power Supplies
Table 34.
Sequencing Relationships for Power Supplies
1. Sequencing relationships are measured from supply to supply and must be maintained under all operating conditions
including power up, power down, power failure, and power state transitions in order to avoid device or system
damage. These relationships can be maintained by propagation of PWRGD signals from one supply rail to the
regulator enable of the next supply. The minimum requirements for a proper system implementation are that:
—
VDDIO ramps such that VDDIO/2 <= VTT.
—
VDD ramps such that VDDIO and VDDA are within spec before VDD is enabled.
—
VLDT ramps such that VDD is within spec before VLDT is enabled.
2. The VTT to VDDIO relationship allows for VTT to power-up before VDDIO.
3. The VDDIO to VTT relationship is critical to avoid overstress of the 2.5-V I/O structures that will occur when VDDIO
exceeds VTT by more than about 1.35 V.
4. The VDDIO to VDD relationship allows for VDDIO to power-up before VDD.
5. The VDDA to VDD relationship allows for VDDA to power-up before VDD. VDDA must power-up before VDD to
ensure that internal clock sources are valid before being used and that clock source multiplexors are properly
controlled.
Power Supply Relationship
Unit
Max
Notes
VTT to VDDIO
V
VTT_dc Max
1, 2
VDDIO to VTT
V
VDDIO_dc Max - VTT_dc Typ
1, 3
VDDIO to VDD
V
VDDIO_dc Max
1, 4
VDDA to VDD
V
VDDA Max
1, 5
VDD to VLDT
V
VDD Max
1, 6
VTT (SUS)
VDDIO (SUS)
VDDIO (RUN)
VDDA (RUN)
VDD (RUN)
VLDT (RUN)
Power Up
S3 Entry
S3 Exit
Power Down
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