參數(shù)資料
型號： AMDOPTERON
英文描述： AMD Opteron - AMD Opteron Processor Data Sheet
中文描述： AMD Opteron處理器- AMD Opteron處理器的數(shù)據(jù)資料
文件頁數(shù)： 45/81頁
文件大小： 1189K
代理商： AMDOPTERON
Chapter 6
Pin Descriptions
45
23932 Rev 3.00 April 2003
AMD Opteron
Processor Data Sheet
6.2
DDR SDRAM Memory Interface Pins
Table 8.
DDR SDRAM Memory Interface Pin Descriptions
Signal Name
Type Description
MEMCLK_UP_H/L[3] O-IOD DRAM Clock connected to DIMM3 for the upper half of the data bus
MEMCLK_UP_H/L[2] O-IOD DRAM Clock connected to DIMM2 for the upper half of the data bus
MEMCLK_UP_H/L[1] O-IOD DRAM Clock connected to DIMM1 for the upper half of the data bus
MEMCLK_UP_H/L[0] O-IOD DRAM Clock connected to DIMM0 for the upper half of the data bus
MEMCLK_LO_H/L[3] O-IOD DRAM Clock connected to DIMM3 for the lower half of the data bus
MEMCLK_LO_H/L[2] O-IOD DRAM Clock connected to DIMM2 for the lower half of the data bus
MEMCLK_LO_H/L[1] O-IOD DRAM Clock connected to DIMM1 for the lower half of the data bus
MEMCLK_LO_H/L[0] O-IOD DRAM Clock connected to DIMM0 for the lower half of the data bus
MEMCKE_UP
O-IOS DRAM Clock Enable
MEMCKE_LO
O-IOS DRAM Clock Enable
MEMDQS[35]
B-IOS DRAM Data Strobe synchronous with MEMCHECK[15:12] for x4 DIMMs.
MEMDQS[34:27]
B-IOS DRAM Data Strobe synchronous with the high-order nibbles of MEMDATA[127:64]
for x4 DIMMs
MEMDQS[26]
B-IOS DRAM data strobe synchronous with MEMCHECK[11:8] for x4 DIMMs and
MEMCHECK[15:8] for x8/x16 DIMMs.
MEMDQS[25:18]
B-IOS DRAM Data Strobe synchronous with the low-order nibbles of MEMDATA[127:64]
for x4 DIMMs and all nibbles for x8/x16 DIMMs
MEMDQS[17]
B-IOS DRAM Data Strobe synchronous with MEMCHECK[7:4] for x4 DIMMs
MEMDQS[16:9]
B-IOS DRAM Data Strobe synchronous with high-order nibbles of MEMDATA[63:0] for x4
DIMMs
MEMDQS[8]
B-IOS DRAM Data Strobe synchronous with MEMCHECK[3:0] for x4 DIMMs and
MEMCHECK[7:0] for x8/x16 DIMMs
MEMDQS[7:0]
B-IOS DRAM Data Strobe synchronous with low-order nibbles of MEMDATA[127:64] for
x4 DIMMs and all nibbles for x8/x16 DIMMs
MEMDATA[127:0]
B-IOS DRAM Interface Data Bus
MEMCHECK[15:0]
B-IOS DRAM Interface ECC Check Bits
MEMCS_L[7:0]
O-IOS DRAM Chip Selects
1
MEMRAS_L
O-IOS DRAM Row Address Select
MEMCAS_L
O-IOS DRAM Column Address Select
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