參數(shù)資料
型號(hào)： AMDOPTERON
英文描述： AMD Opteron - AMD Opteron Processor Data Sheet
中文描述： AMD Opteron處理器- AMD Opteron處理器的數(shù)據(jù)資料
文件頁(yè)數(shù)： 16/81頁(yè)
文件大?。?/td> 1189K
代理商： AMDOPTERON
16
Functional Description
Chapter 2
AMD Opteron
Processor Data Sheet
23932 Rev 3.00 April 2003
2.4.2.1
Memory Pin Interface
The memory controller of the AMD Opteron processor supports registered DDR SDRAM DIMMs.
The following list applies to the pin interface:
The MEMRESET_L pin is required for registered DIMMs and is used to reset the register as
required to support the Suspend to RAM power management state (ACPI S3).
The memory controller can be configured to support either 64-bit or 128-bit memory interfaces.
Refer to Table 1 on page 15 for restrictions based on DDR SDRAM speed.
A 64-bit memory system can support up to four DIMMs, each 64-bits wide
A 128-bit memory system can support up to eight DIMMs, each 64-bits wide, and must be
populated in even numbered pairs as described in the
AMD Opteron
Processor
Motherboard Design Guide
, order# 25180.
Registered DIMMs configured with x4 DRAMs require an additional 16 DQS pins without ECC
support or 18 DQS pins with ECC support. The processor
’
s memory controller provides a total of
36 DQS pins to accommodate this requirement. The additional DQS pins can be connected to the
DIMM Data Mask (DM) pins when connected to x8 or x16 DIMMs (refer to
“
DRAM Operation
”
on page 16 for further details on partial writes and data masking). DIMMs populated with x4
devices normally connect the DRAM Data Mask (DM) pins to VSS.
2.4.2.2
DRAM Operation
At power-on reset, the MEMCKE_LO/UP and MEMRESET_L pins are driven Low while the
processor PLLs are ramping. Clocks are driven on the MEMCLK_LO_H/L[3:0] and
MEMCLK_UP_H/L[3:0] pins only after BIOS programs the appropriate clock ratio value in the
memory controller configuration registers. The actual DRAM frequency may vary for some speeds
based on the CPU clock multiplier, as shown in Table 2 on page 17. Refer to
“
RESET_L and
MEMRESET_L
”
on page 23 for further details on the sequencing of the MEMRESET_L and
MEMCKE_LO/UP pins.
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