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參數(shù)資料
| 型號： | AMDOPTERON |
| 英文描述： | AMD Opteron - AMD Opteron Processor Data Sheet |
| 中文描述： | AMD Opteron處理器- AMD Opteron處理器的數(shù)據(jù)資料 |
| 文件頁數(shù)： | 69/81頁 |
| 文件大小： | 1189K |
| 代理商： | AMDOPTERON |
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Chapter 7
Electrical Data
69
23932 Rev 3.00 April 2003
AMD Opteron
Processor Data Sheet
7.4.2
Power-Up Signal Sequencing
Figure 11 on page 70 illustrates the signal sequencing requirements during a cold reset (power-up
conditions). The actual reset sequencing is defined in the
HyperTransport
I/O Link Specification
.
The following list describes the power-up signal sequencing illustrated in Figure 11. Note that the
numbered items correspond to the numbers in Figure 11.
1. RESET_L must be asserted a minimum of 1 ms prior to the assertion of PWROK, as defined in
the
HyperTransport
I/O Link Specification
. The TMS pin must be asserted a minimum of 10 ns
before PWROK assertion and must be held in the High state a minimum of 10 ns after the
assertion of PWROK.
2. CLKIN_H/L must be within specification at the time the VDD power supply begins to ramp.
3. PWROK is asserted at least 1 ms after CLKIN_H/L is stable and voltages to the processor are
within specification. The processor determines if there are devices attached to its HyperTransport
links 10
μ
s after the assertion of PWROK.
4. After PWROK assertion, the VID[4:0] signals change from the default code (01110b = 1.2 V) to
the value programmed during device manufacturing. The PLL begins locking to the frequency
programmed during device manufacturing 160
μ
s after PWROK is asserted.
5. LDTSTOP_L must be deasserted a minimum of 1
μ
s before the deassertion of RESET_L, as
defined by the
HyperTransport
I/O Link Specification
.
6. The RESET_L signal is deasserted a minimum of 1 ms after PWROK assertion, as defined in the
HyperTransport
I/O Link Specification
. The clocks from the transmitters of all HyperTransport
technology devices must be stable before RESET_L is deasserted.
7. The MEMCLK_LO_H/L[3:0] and MEMCLK_UP_H/L[3:0] signals are stable after BIOS sets the
Memory Clock Ratio Valid (MCR) bit in the processor
’
s DRAM Config Upper register. The
MEMCLK* period is defined by the MEMCLK[2:0] field in the DRAM Config Upper register.
8. MEMRESET_L is deasserted a minimum of 394
μ
s at 166 MHz (DDR333) or a maximum of
655
μ
s at 100 MHz (DDR200) after BIOS sets the Dram_Init bit in the DRAM Config Lower
register. This allows time for the PLL on registered DIMMs to stabilize before the deassertion of
the DIMM
’
s reset signal.
9. The MEMCKE_LO/UP signals are asserted a minimum of 12 MEMCLK* periods following the
deassertion of MEMRESET_L.
Note:
Refer to the
BIOS and Kernel Developer
’
s Guide for the AMD Athlon
64 and
AMD Opteron
Processors,
order# 26094, for details on the memory configuration registers.
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