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參數(shù)資料
| 型號： | AMDOPTERON |
| 英文描述： | AMD Opteron - AMD Opteron Processor Data Sheet |
| 中文描述： | AMD Opteron處理器- AMD Opteron處理器的數(shù)據(jù)資料 |
| 文件頁數(shù)： | 13/81頁 |
| 文件大?。?/td> | 1189K |
| 代理商： | AMDOPTERON |
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Chapter 2
Functional Description
13
23932 Rev 3.00 April 2003
AMD Opteron
Processor Data Sheet
2
Functional Description
2.1
Instruction Set Support
The AMD Opteron
processor supports the standard x86-instruction set defined in the
AMD x86-64
Architecture Programmer
’
s Manual,
volumes 4
–
6, order# 24594. In addition, the processor supports
the following extensions to the standard x86 instruction set, which are described in the same volume
set:
AMD x86-64 instructions
MMX
and 3DNow!
technology instructions
SSE and SSE2 instructions
2.2
Internal Cache Structures
The AMD Opteron processor implements internal caching structures as described in the following
sections.
2.2.1
Level 1 Caches
The L1 data cache (L1 D-Cache) contains 64 Kbytes of storage organized as two-way set associative.
The L1 data cache is protected with ECC. Two simultaneous 64-bit operations (load, store, or
combination) are supported. The L1 instruction cache (L1 I-Cache) contains 64 Kbytes of storage
organized as two-way associative. The L1 instruction cache is protected with parity.
2.2.2
Level 2 Cache
The L2 cache contains both instruction and data stream information. It is organized as 16-way set-
associative. The L2 cache data and tag store is protected with ECC. When a given cache line in the L2
cache contains instruction stream information, the ECC bits associated with the given line are used to
store predecode and branch prediction information.
2.3
Error Handling (Machine Check)
The AMD Opteron processor implements the standard x86 machine check architecture as defined in
the
AMD x86-64 Architecture Programmer
’
s Manual, Volume 2
, order# 24593, and the
BIOS and
Kernel Developer
’
s Guide for the AMD Athlon
64 and AMD Opteron
Processors
,
order# 26094.
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