參數(shù)資料
型號： AMDOPTERON
英文描述： AMD Opteron - AMD Opteron Processor Data Sheet
中文描述： AMD Opteron處理器- AMD Opteron處理器的數(shù)據(jù)資料
文件頁數(shù)： 59/81頁
文件大?。?/td> 1189K
代理商： AMDOPTERON
Chapter 7
Electrical Data
59
23932 Rev 3.00 April 2003
AMD Opteron
Processor Data Sheet
7.3.2
AC Operating Characteristics
1. Write cycle timing parameter
2. The skew consists of pad output skew (+ 250ps) and package routing skew between any two clock pairs (+ 100ps).
3. tCKS Timing Parameter, refer to Figure on page 61.
4. The timing consists of pad output skew (+ 250ps) and package routing skew between any MEMCLK to any MEMDQS
(+ 100ps).
5. tDQS Timing parameter, refer to Figure on page 61.
6. The skew consists of pad output skew (+ 250ps) and package routing skew between any MEMCLK to any MEMDQS
(+ 100ps). Minimum DQS pulse width is 45% of MEMCLK.
7. tDSS, tDSH timing parameters, refer to Figure on page 62.
8. During write, DQ signals are driven quarter clock earlier such that DQS is placed in the center of data eye window.
The skew consists of pad output skew (+ 250ps), package routing skew between any DQS signals and it
’
s associated
DQ signals (+ 75ps) and maximum clock granularity (+ 312.5 ps).
Table 24. Electrical AC Timing Characteristics for DDR SDRAM Signals
Symbol
Parameters
Unit
Min
Typ
Max
Notes
tCK
MEMCLK cycle time
ps
5000
-
10000
15
tCH
MEMCLK high pulse width
ps
0.45*tCK
-
0.55*tCK
tCL
MEMCLK low pulse width
ps
0.45*tCK
-
0.55*tCK
tCKS
MEMCLK output skew
ps
-350
-
350
1,2,3
tDQSH
MEMDQS high pulse width
ps
0.45*tCK
-
0.55*tCK
1
tDQSL
MEMDQS low pulse width
ps
0.45*tCK
-
0.55*tCK
1
tDQS
MEMCLK to MEMDQS
ps
-350
-
350
1,4,5
tDSS
MEMDQS falling edge to MEM-
CLK rising edge
ps
0.45*tCK -
350
-
-
1,6,7
tDSH
MEMCLK rising edge to MEM-
DQS falling edge
ps
0.45*tCK -
350
-
-
1,6,7
tDQSQV
MEMDQS to MEMDATA shift
(when data becomes valid)
ps
-{0.5*
tDQSHmax -
[638]}
-
-{0.5*
tDQSHmin
+ [638]}
1,8,9
tDQSQIV
MEMDQS to MEMDATA shift
(when data becomes invalid)
ps
{0.5*tDQSH-
min - [638]}
-
{0.5*
tDQSHmax
+ [638]}
1,8,9
t2
MEMADD/CMD to MEMCLK
(Registered DIMM environment -
MEMADD/CMD are launched 1/2
clock early)
ps
- 350
-
350
1,10,11
t3
MEMDATA edge arrival relative
to MEMDQS
ps
-{tCK/4 -
[350+0.2*
(tCK/4)]}
-
tCK/4 -
[350+0.2*
(tCK/4)]
12,13,14
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