參數(shù)資料
型號： AMDOPTERON
英文描述： AMD Opteron - AMD Opteron Processor Data Sheet
中文描述： AMD Opteron處理器- AMD Opteron處理器的數(shù)據(jù)資料
文件頁數(shù)： 14/81頁
文件大?。?/td> 1189K
代理商： AMDOPTERON
14
Functional Description
Chapter 2
AMD Opteron
Processor Data Sheet
23932 Rev 3.00 April 2003
The machine check architecture is defined with ECC single-bit detection/correction and double-bit
detection for the following arrays:
L1 Data Cache Storage
L2 Data Cache Storage
L2 Data Cache Tag
Instruction Cache
DRAM. See
“
Memory Controller
”
on page 14.
2.4
Northbridge
The Northbridge logic in the AMD Opteron processor refers to the HyperTransport
technology
interface and the memory controller and their respective interfaces to the CPU cores. These interfaces
are described in more detail in the following sections.
2.4.1
HyperTransport
Technology Overview
The AMD Opteron processor includes three 16-bit HyperTransport technology interfaces capable of
operating up to 1600 mega-transfers per second (MT/s) with a resulting bandwidth of up to 6.4
Gbytes/s (3.2 Gbytes/s in each direction). The AMD Opteron processor supports HyperTransport
technology synchronous clocking mode. Refer to the
HyperTransport
I/O Link Specification
(www.hypertransport.org) for details of link operation.
2.4.1.1
Link Initialization
The
HyperTransport
I/O Link Specification
details the negotiation that occurs at power-on to
determine the widths and rates used with the link. Refer also to the
BIOS and Kernel Developer
’
s
Guide for the AMD Athlon
64 and AMD Opteron
Processors
,
order# 26094, for information
about link initialization and setup of routing tables.
Refer to the
AMD Opteron
Processor Motherboard Design Guide
, order# 25180, for details on the
proper HyperTransport technology signal termination resistor values.
2.4.1.2
HyperTransport
Technology Transfer Speeds
The HyperTransport link of the AMD Opteron processor is capable of operating at 400, 800, 1200,
and 1600 MT/s. The link transfer rate is determined during the software configuration of the system,
as specified in the
HyperTransport
I/O Link Specification
.
2.4.2
Memory Controller
The processor
’
s memory controller provides a programmable interface to a variety of standard
registered DDR SDRAM DIMM configurations. The following features are supported:
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