參數(shù)資料
型號： AMDOPTERON
英文描述： AMD Opteron - AMD Opteron Processor Data Sheet
中文描述： AMD Opteron處理器- AMD Opteron處理器的數(shù)據(jù)資料
文件頁數(shù)： 22/81頁
文件大?。?/td> 1189K
代理商： AMDOPTERON
22
Power Management
Chapter 3
AMD Opteron
Processor Data Sheet
23932 Rev 3.00 April 2003
If a STPCLK assertion message is received while the processor is in the Halt state, the processor
enters the Stop Grant state and issues a Stop Grant special cycle. When a STPCLK deassertion
message is received, the processor exits the Stop Grant state and returns to the Halt state.
The processor exits the Halt state in response to PWROK deassertion, RESET_L assertion, INIT,
NMI, SMI, or any unmasked interrupt received over the HyperTransport link.
3.2
STPCLK/Stop Grant
When the processor recognizes the STPCLK assertion message, it enters the Stop Grant state on the
next instruction boundary and issues a Stop Grant special cycle. The power savings associated with
the Stop Grant state are determined by configuration registers in the processor. The power savings
mechanisms associated with the Stop Grant state include the following:
CPU clock grid divisor applied in the absence of probe activity. If probe activity that requires a
cache snoop occurs while the processor is in the Stop Grant state, the clock grid is ramped back up
to service the probe. When probe activity ceases, the CPU clock grid is ramped back down again.
Placing system memory into self-refresh mode in response to LDTSTOP_L signal assertion.
Ramping the processor host bridge/memory controller clock grid down in response to
LDTSTOP_L signal assertion.
Changing HyperTransport link width and/or link frequency in response to LDTSTOP_L signal
assertion.
The processor exits the Stop Grant state when it receives the following:
A STPCLK deassertion message.
RESET_L pin asserted or an INIT assertion message.
PWROK is deasserted.
If the LDTSTOP_L signal is asserted after the processor is in the Stop Grant state, then LDTSTOP_L
must be deasserted, and the HyperTransport link must be re-initialized before a STPCLK deassertion
message can be received by the processor to bring the processor out of the Stop Grant state.
The processor
’
s host bridge ensures that STPCLK messages are passed to the CPU prior to the
subsequent I/O response to the cycle that caused STPCLK assertion as long as the subsequent I/O
response message has the PassPW bit clear and the Unit ID of the response matches the Unit ID of the
STPCLK message.
3.3
PWROK
When PWROK is deasserted, the processor performs the following steps:
Isolates its VDDIO- and VTT-powered logic from all other internal logic to prevent leakage
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