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參數(shù)資料
| 型號： | AMDOPTERON |
| 英文描述： | AMD Opteron - AMD Opteron Processor Data Sheet |
| 中文描述： | AMD Opteron處理器- AMD Opteron處理器的數(shù)據(jù)資料 |
| 文件頁數(shù)： | 19/81頁 |
| 文件大?。?/td> | 1189K |
| 代理商： | AMDOPTERON |
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Chapter 2
Functional Description
19
23932 Rev 3.00 April 2003
AMD Opteron
Processor Data Sheet
2.4.2.4
Chip Kill
The memory controller contains the ability to continuously correct 4-bit errors from a failed x4
memory device across the 128-bit wide data path. This feature optionally takes the place of normal
ECC error detection and correction. Operating the memory controller with Chip Kill enabled will
result in a two clock latency penalty on memory access due to the detection, correction, and data
containment overhead of operating in this mode.
2.4.2.5
Main Memory Hardware Scrubbing
The memory controller scrubs the main memory arrays to prevent the build up of soft errors. Any
correctable or non-correctable errors are logged to the machine check logs and can be programmed to
invoke the machine check interrupt. The scrubbing function can be used in three modes as described
in the following sections.
2.4.2.5.1
Progressive Scrubbing
In this mode, the scrubber progressively proceeds through main memory, performing a read-write
cycle or a read-modify-write cycle if a correctable single-bit error is found. The scrubber scrubs one
cache line on each scrub interval that is programmable from 40 ns to 84 ms.
2.4.2.5.2
Source Correction Scrubbing
In this mode, the scrubber does not progressively proceed through main memory but is directed to
scrub any cache line that is the source of any corrected single bit error. During normal operation,
single-bit errors are corrected on the fly and the corrected data is passed without updating the source
memory location. This mode of scrubbing sets the scrubber to then correct the source memory
location, as well.
2.4.2.5.3
Progressive Plus Source Correction Scrubbing
In this mode, the scrubber progressively proceeds through main memory as in progressive mode, but
the current cache line location is changed to that of the source of any corrected single bit error. The
progressive scrubbing then continues from that location.
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