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參數資料
| 型號： | AM79C974KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數： | 81/153頁 |
| 文件大?。?/td> | 838K |
| 代理商： | AM79C974KCW |
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P R E L I M I N A R Y
AMD
81
Am79C974
Illegal command code issued
The target disconnects from the SCSI bus
SCSI bus service request
Successful completion of a command
The Am79C974 has been reselected
The Fast SCSI Block
The functionality of the SCSI block is described in the
following section. Topics to be covered are:
SCSI Block ID
SCSI FIFO Threshold
Data Transmission
REQ
/
ACK
Control
Parity
Reset Levels
SCSI Block ID
The Am79C974 contains a SCSI Block ID code which is
stored in the MSB of the Current Transfer Count Regis-
ter. The code reflects the chip’s revision level and family
code. This 8-bit code may be read when the following
conditions are true.
After power up or a chip reset has occurred
Before the Current Transfer Counter ((B)+38h) is
loaded
The part-unique ID code in Register ((B)+38h) will read
as follows:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
1
0
0
1
0
SCSI FIFO Threshold
The threshold value for the SCSI FIFO is two bytes (one
word). When this threshold is reached, the SCSI block
will indicate to the DMA engine that it is capable of re-
ceiving or sending data bytes.
Data Transmission
Data transmission rates will vary from system to system,
depending on the number of devices configured on the
SCSI bus, as well as the transfer rates that each individ-
ual device is capable of sustaining.
Transfer rates for the Am79C974 are controlled by the
FASTSCSI and FASTCLK bits in Control Register
Three, as well by the Extended Timing Feature in Con-
trol Register One.
To achieve 10 Mbyte/s transmission rates, the following
conditions must be true:
A 40 MHz clock (50% duty cycle) must be supplied
to SCSICLK.
The target must be able to sustain Fast SCSI
timings.
Bits 3 (FASTCLK) and 4 (FASTSCSI) in Control
Register Three must be set to ‘1.’
The lower three bits of Register ((B)+24h), the
Clock Conversion Factor Register must be
programmed to ‘000.’
The lower 5 bits of the Synchronous Transfer
Period Register ((B)+18h) must be set to a value
of ‘04h.’
The FASTCLK and FASTSCSI bits in Control Register
Three modify the SCSI state machine to produce both
FAST and Normal SCSI timings. Synchronous data
transmission rates are dependent on the input clock fre-
quency selected, as well as the transfer period.
Bits 4:0 in the Synchronous Transfer Period Register
((B)+18h) specify the period for synchronous data trans-
fers. For programming information, refer to the Techni-
cal Manual.
REQ
/
ACK
Control
The assertion and deassertion time for the
REQ
and
ACK
signals may be controlled via the Synchronous Off-
set Register ((B)+1Ch). Bits 7:6 control
REQ
/
ACK
deassertion delay with respect to the time that data is
valid, while bits 5:4 control
REQ
/
ACK
assertion delay.
The deassertion for
REQ
/
ACK
may be moved ahead .5
clock cycles, or it may be delayed for up to 1.5 clock cy-
cles. Deassertion delay options depend on the status of
the FASTCLK bit in Control Register Three. Assertion
delay for
REQ
/
ACK
can vary from 0 to 1.5 clock cycles.
Parity
Parity on the SCSI bus is such that the total number of
logical ones on data bus including the parity bit must be
odd. Parity checking features are implemented via two
bits in the Status Register and Control Register One.
Parity checking can be implemented on data flowing in
from the SCSI bus. Parity is always generated internally
by the Am79C974 for data moving onto the SCSI bus.
Feature
Parity From
SCSI
Bit Name
Parity Error
Reporting
Bit #
4
Register
Control
Reg One
((B)+20h)
Status
Register
((B)+10h)
Parity Status
Parity Error
5
Parity Checking on the SCSI Bus
The Parity Error Reporting Bit (Bit 4, Control Register
One) enables parity checking on all incoming bytes from
the SCSI bus. This feature is cleared to ‘0’ by a hardware
reset.
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相關代理商/技術參數 |
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| AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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