- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C974KCW (ADVANCED MICRO DEVICES INC) PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems PDF資料下載
參數(shù)資料
| 型號： | AM79C974KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 78/153頁 |
| 文件大?。?/td> | 838K |
| 代理商： | AM79C974KCW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁當前第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁
AMD
P R E L I M I N A R Y
78
Am79C974
Command Register (CMD)
The upper 3 bytes of Command register are reserved,
the remaining (LSB) byte is defined as follows:
Address (B)+40h, LSB
7
6
READ/WRITE
1
DIR
INTE_D
INTE_P
MDL
Reserved Reserved
CMD1
CMD0
5
4
3
2
0
DIR:
Data transfer direction bit. When this bit is set, the direc-
tion of transfer is from SCSI to memory.
INTE_D:
DMA transfer active interrupt enable bit. When this bit is
set, the ERROR or DONE condition will cause
INTA
to
be asserted.
INTE_P:
Page transfer active interrupt bit.
MDL:
Memory Descriptor List (MDL) SPA enable bit.
RESERVED:
Reserved for future expansion. The zero value must be
written in these bits.
CMD1-0:
These two bits are encoded to represent four com-
mands: IDLE, BLAST, START, and ABORT.
CMD1
0
CMD0
0
Command
IDLE
Description
Resets the DMA block to the IDLE state. Stops any current transfer. Does not
affect status bits or cause an interrupt.
Empties all data bytes in DMA FIFO to memory during a DMA
write operation. Upon completion, the ‘BCMPLT’ bit will be set
in the DMA Status register. This command should not be used
during a DMA read operation.
Terminates the current DMA transfer. Restores the DMA engine to the IDLE
state. Sets the ABORT bit (bit 2) in the status register.
Note: This is only valid after a ‘START’ command is issued.
Initiates a new DMA transfer. These bits must remain set
throughout the DMA operation until the ‘DONE’ bit in the DMA
Status Register is set.
Note: This command should be issued only after all other
control bits have been initialized.
0
1
BLAST
1
0
ABORT
1
1
START
DMA Scatter-Gather Mechanism
The Am79C974 controller contains a scatter-gather
translation mechanism which facilitates faster data
transfers. This feature uses a
M
emory
D
escriptor
L
ist
which is stored in system memory. Use of the Memory
Descriptor List allows a single SCSI transfer to be read
from (or written to) non-contiguous physical memory lo-
cations. This mechanism avoids copying the transfer
data and MDL list, which was previously required for
conventional DMA operations.
Memory Descriptor List (MDL)
The MDL is a non-terminated (no End Of File marker)
list of 32-bit page frame addresses, which is always
aligned on a Double Word boundary. The format is
shown below:
31
12 11
0
Page Frame Address
Ignored
DMA Scatter-Gather Operation
(4k aligned elements)
The scatter-gather mechanism described below
assumes 4k page alignment and size for all MDL entries
except the first and last entry. This feature is enabled by
setting the MDL bit in the DMA Command register (Bit 4,
Address (B)+40h).
1. a) Prepare the Memory Descriptor List (MDL)
through software and store it in system
memory.
b) Load the address of the starting entry in the
Memory Descriptor List (MDL) into the Start
Memory Descriptor List Address (SMDLA)
register. This value is automatically copied into
the Working MDL Address Counter (WMAC).
c) Program the Starting Transfer Count (STC)
register with the total transfer length (i.e., # of
bytes). Also program the Starting Physical
Address (SPA) register (bits 11:0) with the
starting offset of the first entry.
Note
: The value in the SMDLA register must be double
word aligned. Therefore, read/write transactions will al-
ways begin on a double word boundary.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C975 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973 | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975KCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C973VCW | PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。