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參數(shù)資料
| 型號(hào)： | AM79C974KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 20/153頁 |
| 文件大?。?/td> | 838K |
| 代理商： | AM79C974KCW |
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AMD
P R E L I M I N A R Y
20
Am79C974
When
RST
is active,
GNTB
is an input for NAND tree
testing.
IDSELA
Initialization Device Select
Input, Active High
This signal is used as a SCSI controller selection for the
Am79C974
during
configuration
write transaction.
read
and
When
RST
is active, IDSELA is an input for NAND tree
testing.
IDSELB
Initialization Device Select
Input, Active High
This signal is used as an Ethernet controller selection for
the PCnet-SCSI controller during configuration read
and write transaction.
When
RST
is active, IDSELB is an input for NAND tree
testing.
INTA
Interrupt Request
Input/Output, Active Low, Open Drain
This signal combines the interrupt requests from both
the SCSI DMA engine and the SCSI core. The interrupt
source can be determined by reading the SCSI DMA
Status Register. It is cleared when the Status Register is
read.
When
RST
is active,
INTA
is an input for NAND tree test-
ing. This is the only time
INTA
is an input.
INTB
Interrupt Request
Input/Output, Active Low, Open Drain
An asynchronous attention signal which indicates that
one or more of the following status flags is set: BABL,
MISS, MERR, RINT, IDON, RCVCCO, RPCO, JAB,
MPCO, or TXSTRT. Each status flag has a mask bit
which allows for suppression of
INTB
assertion. The
flags have the following meaning:
BABL
RCVCCO
RPCO
JAB
MISS
MERR
MPCO
RINT
IDON
TXSTRT
Babble
Receive Collision Count Overflow
Runt Packet Count Overflow
Jabber
Missed Frame
Memory Error
Missed Packet Count Overflow
Receive Interrupt
Initialization Done
Transmit Start
When
RST
is active,
INTB
is an input for NAND tree
testing. This is the only time
INTB
is an input.
IRDY
Initiator Ready
Input/Output, Active Low
This signal indicates PCnet-SCSI controller’s ability, as
a master device, to complete the current data phase of
the transaction.
IRDY
is used in conjunction with the
TRDY
. A data phase is completed on any clock when
both
IRDY
and
TRDY
are asserted. During a write
IRDY
indicates that valid data is present on AD[31:00]. During
a read
IRDY
indicates that data is accepted by the
PCnet-SCSI controller as a bus master. Wait states are
inserted until both
IRDY
and
TRDY
are asserted simul-
taneously.
When
RST
is active,
IRDY
is an input for NAND tree
testing.
LOCK
Lock
Input, Active Low
LOCK
is used by the current bus master to indicate an
atomic operation that may require multiple transfers.
As a slave device, the PCnet-SCSI controller can be
locked by any master device. When another master at-
tempts to access the PCnet-SCSI while it is locked, the
PCnet-SCSI controller will respond by asserting
DEVSEL
and
STOP
with
TRDY
deasserted (PCI retry).
The PCnet-SCSI controller will never assert
LOCK
as a
master.
When
RST
is active,
LOCK
is an input for NAND tree
testing.
PAR
Parity
Input/Output, Active High
Parity is even parity across AD[31:00] and C/
BE
[3:0].
When the PCnet-SCSI controller is a bus master, it
generates parity during the address and write data
phases. It checks parity during read data phases. When
the PCnet-SCSI controller operates in slave mode and
is the target of the current cycle, it generates parity dur-
ing read data phases. It checks parity during address
and write data phases.
When
RST
is active, PAR is an input for NAND tree
testing.
PERR
Parity Error
Input/Output, Active Low, Open Drain
This signal is asserted for one CLK by the PCnet-SCSI
controller when it detects a parity error during any data
phase when its AD[31:00] lines are inputs. The
PERR
pin is only active when PERREN (bit 6) in the PCI com-
mand register is set.
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