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參數(shù)資料
| 型號(hào)： | AM79C974KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 77/153頁 |
| 文件大?。?/td> | 838K |
| 代理商： | AM79C974KCW |
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P R E L I M I N A R Y
AMD
77
Am79C974
Logic block via a 32-bit data bus, and the funnel logic
properly reduces this stream of data to a 16-bit stream to
properly interface with the SCSI FIFO.
96-Byte
DMA FIFO
Funnel
Logic
16-Byte
SCSI FIFO
32
16
18681A-30
Figure 26. DMA FIFO to SCSI FIFO Interface
SCSI DMA Programming Sequence
The following section outlines the procedure for execut-
ing SCSI DMA operations:
1. Issue IDLE command to the DMA Engine
2. Configure the SCSI block registers (e.g. synchro-
nous operation, offset values, etc.)
3. Program the DMA registers to set up address and
transfer count
4. Issue a transfer command to the SCSI command
registers
5. Issue the START command to the DMA engine
6. At the end of the DMA transaction, issue the IDLE
command to the DMA engine
Memory Descriptor List (MDL) Based DMA
Programming
The following section outlines the use of the MDL for
scatter-gather DMA operations:
1. Set up the MDL list
2. Use the programming sequence defined earlier for
initiating a SCSI DMA transfer
DMA Registers
The following is a summary of the DMA register set or
the DMA Channel Context Block (DMA CCB). These
registers control the specifics for DMA operations such
as transfer length and scatter-gather options. The three
read-only working counter registers allow the system
software and driver to monitor the DMA transaction.
Each register address is represented by the PCI Con-
figuration Base Address (B) and its corresponding offset
value. The Base address for the SCSI controller is
stored at register address (10h) in the SCSI PCI configu-
ration space.
Table 6. The DMA Registers
Register Acronym
Addr (Hex)
Register Description
Command
(bits 31:8 reserved, bits 7:0 used)
Starting Transfer Count
(bits 31:24 reserved, bits 23:0 used)
Starting Physical Address
(bits 31:0 used)
Working Byte Counter
Working Address Counter
(bits 31:0 used)
Status Register
(bits 31:8 reserved, bits 7:0 used)
Starting Memory Descriptor List (MDL) Address
Working MDL Counter
Type
CMD
(B)+40
R/W
STC
(B)+44
R/W
SPA
WBC
(B)+48
(B)+4C
R/W
R
WAC
(B)+50
R
STATUS
SMDLA
WMAC
(B)+54
(B)+58
(B)+5C
R
R/W
R
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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