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參數(shù)資料
| 型號： | AM79C974KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 54/153頁 |
| 文件大?。?/td> | 838K |
| 代理商： | AM79C974KCW |
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AMD
P R E L I M I N A R Y
54
Am79C974
the controller portion of the Am79C974 controller sees
the first ISRDCLK transition. This also strobes in the in-
coming fifth bit to the MENDEC as Manchester “1”.
IRXDAT may make a transition after the ISRDCLK rising
edge in bit cell 5, but its state is still undefined. The
Manchester “1” at bit 5 is clocked to IRXDAT output at
1/4 bit time in bit cell 6.
PLL Tracking
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
rection circuit. This circuit ensures that the phase-
locked clock remains locked on the received signal.
Individual bit cell phase corrections of the Voltage Con-
trolled Oscillator (VCO) are limited to 10% of the phase
difference between BCC and phase-locked clock.
Hence, input data jitter is reduced in ISRDCLK by
10to1.
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI
±
inputs after
IRXCRS is asserted for an end of message. IRXCRS
de-asserts 1 to 2 bit times after the last positive transi-
tion on the incoming message. This initiates the end of
reception cycle. The time delay from the last rising edge
of the message to IRXCRS de-assert allows the last bit
to be strobed by ISRDCLK and transferred to the con-
troller section, but prevents any extra bit(s) at the end
ofmessage.
Data Decoding
The data receiver is a comparator with clocked output to
minimize noise sensitivity to the DI
±
inputs. Input error is
less than
±
35 mV to minimize sensitivity to input rise and
fall time. ISRDCLK strobes the data receiver output at
1/4 bit time to determine the value of the Manchester bit,
and clocks the data out on IRXDAT on the following
ISRDCLK. The data receiver also generates the signal
used for phase detector comparison to the internal
MENDEC voltage controlled oscillator (VCO).
Differential Input Terminations
The differential input for the Manchester data (DI
±
)
should be externally terminated by two 40.2
±
1% re-
sistors and one optional common-mode bypass capaci-
tor, as shown in the Differential Input Termination
diagram below. The differential input impedance, Z
IDF
,
and the common-mode input impedance, Z
ICM
, are
specified so that the Ethernet specification for cable ter-
mination impedance is met using standard 1% resistor
terminators. If SIP devices are used, 39
is the nearest
usable value. The CI
±
differential inputs are terminated
in exactly the same way as the DI
±
pair.
18681A-24
Am79C974
DI+
DI-
40.2
40.2
0.01
μ
F
to
0.1
μ
F
AUI Isolation
Transformer
Figure 20.
Differential Input Termination
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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