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參數(shù)資料
| 型號(hào)： | AM79C974KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnetTM-SCSI Combination Ethernet and SCSI Controller for PCI Systems |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁數(shù)： | 75/153頁 |
| 文件大?。?/td> | 838K |
| 代理商： | AM79C974KCW |
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P R E L I M I N A R Y
AMD
75
Am79C974
SCSI Controller
The primary function of the PCnet-SCSI controller is to
transfer data between the 4 byte-wide PCI bus and 1
byte-wide SCSI bus. The controller consists of two
blocks: SCSI and DMA. The SCSI block sits between
the SCSI bus and the DMA block. It controls data flow
to/from SCSI bus. The DMA block is located between
the SCSI block and the PCI bus Interface Unit. It handles
data flow to/from PCI bus.
The operation of each block is governed by a set of con-
trol registers:
1. Channel Context Block (CCB) registers control the
DMA block
2. SCSI registers control the SCSI block
In a normal operation, both sets of registers must be pro-
grammed with the specifics of the transfer, such as start-
ing address, transfer count, etc. (For more information,
refer to Technical ManualPID #18738A).
SCSI Specific DMA Engine
The SCSI Specific DMA Engine in the Am79C974 pro-
vides bus-mastering capabilities to allow flexibility and
performance advantages over slave PCI-SCSI devices.
Built into the engine is a 96-byte (24 DWORD) FIFO and
additional logic to handle the transition between the
32-bit PCI bus and the 8-bit SCSI bus.
Figure 25 illustrates the DMA Engine in relation to the
PCI interface and the SCSI block. As its most basic func-
tion, the DMA engine acts as the DMA controller in a bus
master capacity on the PCI bus, transferring data be-
tween memory and the SCSI block. All Command, Data,
Status, and Message bytes pass through the DMA FIFO
on their way to or from the SCSI bus. However, for pro-
grammed I/O (PIO) accesses to the SCSI registers, the
DMA FIFO is bypassed as data moves directly from the
SCSI block to the PCI interface. Since PIO operations
do not pass through the funneling logic and DMA FIFO,
data is transferred one byte at a time from the SCSI
block to the PCI interface via the least significant byte
lane. (The three most significant byte lanes will contain
null data.)
18681A-29
PCI
Bus
Interface
Unit
Funnel/Alignment
Empty
Logic
SCSI
FIFO
(16x9)
DREQ
DACK
SCSI Block
DMA
CNTL
Full
Data
Path
Unit
PCI^GNT
AD(3:0)
CS
RD
WR
AD(4:0),
CS
WR
,
RD
,
32
16
32
Data
Data
Data
PCI
Config
Space
AD (4:0)
C/
BE
(3:0)
PCI^REQ
DMA
REG
SCSI REG
DMA Engine
8 Data
DMA
FIFO
(24x32)
Figure 25. PCI BIU – DMA Engine – SCSI Block
Since the PCI bus is 4 bytes wide and the SCSI bus is
only 1 byte wide, funneling logic is included in this en-
gine to handle byte alignment and to ensure that data is
properly transferred between the SCSI bus and the
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C975 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet⑩-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
| AM79C975BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C975BKD\W | 制造商:Advanced Micro Devices 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY 制造商:AMD (Advanced Micro Devices) 功能描述:PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY |
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