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參數資料
| 型號： | AM79C970AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數： | 90/219頁 |
| 文件大小： | 1065K |
| 代理商： | AM79C970AVCW |
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AMD
P R E L I M I N A R Y
90
Am79C970A
the EADISEL bit of BCR2 is set to ONE and the PCnet-
PCI II controller is programmed to promiscuous mode
(PROM bit of the Mode Register is set to ONE), then all
incoming frames will be accepted, regardless of any ac-
tivity on the
EAR
pin.
Internal address match is disabled when PROM
(CSR15, bit 15) is cleared to ZERO, DRCVBC (CSR15,
bit 14) and DRCVPA (CSR15, bit 13) are set to ONE and
the Logical Address Filter registers (CSR8 to CSR11)
are programmed to all ZEROs.
When the EADISEL bit of BCR2 is set to ONE and inter-
nal address match is disabled, then all incoming frames
will be accepted by the PCnet-PCI II controller, unless
the
EAR
pin becomes active during the first 64 bytes of
the frame (excluding preamble and SFD). This allows
external address lookup logic approximately 58 byte
times after the last destination address bit is available to
generate the
EAR
signal, assuming that the PCnet-PCI
II controller is not configured to accept runt packets. The
EADI logic only samples
EAR
from 2 bit times after SFD
until 512 bit times (64 bytes) after SFD. The frame will be
accepted if
EAR
has not been asserted during this win-
dow. If Runt Packet Accept (CSR124, bit 3) is enabled,
then the
EAR
signal must be generated prior to the re-
ceive message completion, if frame rejection is to be
guaranteed. Runt packet sizes could be as short as 12
byte times (assuming 6 bytes for source address, 2
bytes for length, no data, 4 bytes for FCS) after the last
bit of the destination address is available.
EAR
must
have a pulse width of at least 110 ns.
Note that when the PCnet-PCI II controller is operating
in full-duplex mode or runt packet accept is turned on
(CSR124, bit 3) the Receive FIFO Watermark (CSR80,
bits 13–12) must be programmed to 64 (01b) or 128
(10b) to allow the full window of 512 bit times after SFD
for the assertion of
EAR
. If the watermark was pro-
grammed to 16 (00b), receive FIFO DMA could start be-
fore
EAR
is asserted to reject the frame.
The EADI outputs continue to provide data throughout
the reception of a frame. This allows the external logic
to capture frame header information to determine
protocol type, inter-networking information, and other
useful data.
The EADI interface will operate as long as the STRT bit
in CSR0 is set, even if the receiver and/or transmitter
are disabled by software (DTX and DRX bits in CSR15
are set). This configuration is useful as a semi-power-
down mode in that the PCnet-PCI II controller will not
perform any power-consuming DMA operations. How-
ever, external circuitry can still respond to control
frames on the network to facilitate remote node control.
The table below summarizes the operation of the
EADI interface:
Table 11. EADI Operations
PROM
EAR
Required Timing
Received Messages
1
X
No timing requirements
All received frames
0
1
No timing requirements
All received frames
0
0
Low for 110 ns during the window from
2 bits after SFD to 512 bits after SFD
PCnet-PCI II controller internal physical
address and logical address filter
matches and broadcast frames
Expansion ROM Interface
The Expansion ROM is an 8-bit ROM connected to the
PCnet-PCI II controller Expansion ROM Data bus
(ERD). It can be of up to 64 Kbytes in size. The Expan-
sion ROM Address bus (ERA) is 8 bits wide. An external
latch is required to store the upper 8 bits of the 16-bit ad-
dress to the ROM. All ERA outputs are forced to a con-
stant level to conserve power while no access to the
Expansion ROM is performed.
EROE
is asserted during the Expansion ROM read op-
eration. This signal can be used to control the
OE
input
of the ROM. In an application that does not use the GPSI
port, EROE can be left unconnected and the
OE
input of
the ROM can be tied to ground to always enable the
ROM data outputs. The
CE
input of the ROM can either
be tied to ground or it can also be connected to EROE.
The signal ERACLK is provided to strobe the upper 8
bits of the address into an external latch. The timing rela-
tion of ERACLK to ERA is such that both ’373 (transpar-
ent latch) and ’374 (D flip-flop) types of address latch
can be used.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AM79C970AVI\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AVI\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AVIW | 制造商:Rochester Electronics LLC 功能描述: |
| AM79C970AVW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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