參數(shù)資料
型號： AM79C970AVCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： TQFP-144
文件頁數(shù)： 153/219頁
文件大?。?/td> 1065K
代理商： AM79C970AVCW
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P R E L I M I N A R Y
AMD
153
Am79C970A
BCR17: I/O Base Address Upper
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 IOBASEU
Reserved
H_RESET, the value in this
register will be undefined. The
setting of this register has no ef-
fect on any PCnet-PCI II control-
ler function. It is only included for
software compatibility with other
PCnet family devices.
locations.
After
Read/Write accessible always.
IOBASEU is not affected by
S_RESET or by setting the
STOP bit.
BCR18: Burst and Bus Control Register
Bit
Name
Description
Note that bits 15–0 in this register
are programmable through the
external EEPROM. Reserved
bits and read-only bits should be
programmed to ZERO.
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–12ROMTMG
Expansion ROM Timing. The
value of ROMTMG is used to
tune the timing of the Expansion
ROM interface. ROMTMG de-
fines the time from when the
PCnet-PCI II controller drives
ERA[7:0] with the lower 8-bits of
the Expansion ROM address to
when the PCnet-PCI II controller
latches in the data on the
ERD[7:0] inputs. The register
value specifies the time in num-
ber of clock cycles. A ROMTMG
value of ZERO results in the
same timing as a ROMTMG
value of ONE.
The access time for the Expan-
sion ROM device (t
ACC
) can be
calculated by subtracting the
clock to output delay for the
ERA[7:0] outputs (t
VAL
(ERA)) and
the input to clock setup time for
the ERD[7:0] inputs (t
SU
(ERD))
from the time defined by
ROMTMG:
t
ACC
≤
ROMTMG * clock period –
t
VAL
(ERA) – t
SU
(ERD)
For an adapter card application,
the value used for clock period
should be 30 ns to guarantee cor-
rect interface timing at the maxi-
mum clock frequency of 33 MHz.
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
ROMTMG is set to the value of
1001b by H_RESET and is not
affected by S_RESET or by
setting the STOP bit. The default
value allows using an Expansion
ROM with an access time of 250
ns in a system with a maximum
clock frequency of 33 MHz.
11–10
RES
Reserved locations. Written as
ZEROs and read as undefined.
9
MEMCMD
Memory Command. This bit de-
termines the command code
used for burst read accesses
to
transmit
buffers.
MEMCMD is cleared to ZERO,
all burst read accesses to trans-
mit buffers are of the PCI com-
mand type Memory Read Line
(type 14). When MEMCMD is set
to ONE, all burst read accesses
to transmit buffers are of the PCI
command type Memory Read
Multiple (type 12).
When
Read accessible always. Write
accessible only when either
the STOP or the SPND bit is
set. MEMCMD is cleared by
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
8
EXTREQ
Extended Request. This bit
controls the deassertion of
REQ
for a burst transaction. If EX-
TREQ is cleared to ZERO,
REQ
is deasserted at the beginning of
a burst transaction. (The PCnet-
PCI II controller never performs
more than one burst transaction
within a single bus mastership
period.) In this mode, the PCnet-
PCI II controller relies on the PCI
Latency Timer to get enough bus
bandwidth, in case the system
arbiter also removes
GNT
at the
beginning of the burst transac-
tion. If EXTREQ is set to ONE,
REQ
stays asserted until the next
to last data phase of the burst
transaction is done. This mode is
useful for systems that imple-
ment an arbitration scheme with-
out preemption and require that
REQ
stays asserted throughout
the transaction.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970AVI\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
AM79C970AVI\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
AM79C970AVIW 制造商:Rochester Electronics LLC 功能描述:
AM79C970AVW 制造商:Rochester Electronics LLC 功能描述:- Bulk
AM79C970AWW WAF 制造商:Advanced Micro Devices 功能描述:
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