![](http://datasheet.mmic.net.cn/260000/AM79C970AKCW_datasheet_15869128/AM79C970AKCW_134.png)
AMD
P R E L I M I N A R Y
134
Am79C970A
CSR64: Next Transmit Buffer Address Lower
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0
NXBAL
Contains the lower 16 bits of the
next transmit buffer address from
which the PCnet-PCI II controller
will transmit an outgoing frame.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
accessible
only
CSR65: Next Transmit Buffer Address Upper
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 NXBAU
Contains the upper 16 bits of the
next transmit buffer address from
which the PCnet-PCI II controller
will transmit an outgoing frame.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
accessible
only
CSR66: Next Transmit Byte Count
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–12
RES
Reserved locations. Read and
written as ZEROs.
11–0
NXBC
Next Transmit Byte Count. This
field is a copy of the BCNT field
of TMD1 of the next transmit
descriptor.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
accessible
only
CSR67: Next Transmit Status
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0
NXST
Next Transmit Status. This field
is a copy of bits 31–16 of TMD1 of
the next transmit descriptor.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
accessible
only
7–0
RES
Reserved locations. Read and
written as ZEROs. Accessible
only when either the STOP or the
SPND bit is set.
CSR72: Receive Descriptor Ring Counter
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 RCVRC
Receive Descriptor Ring Counter
location. Contains a two’s com-
plement binary number used to
number the current receive de-
scriptor. This counter interprets
the value in CSR76 as pointing to
the first descriptor. A counter
value of ZERO corresponds to
the last descriptor in the ring.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
accessible
only
CSR74: Transmit Descriptor Ring Counter
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 XMTRC
Transmit
Counter location. Contains a
two’s complement binary num-
ber used to number the current
Descriptor
Ring