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參數(shù)資料
| 型號(hào)： | AD9520-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 68/76頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN EXT VCO 64LFCSP |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9520-5
Data Sheet
Rev. A | Page 70 of 76
Table 55. EEPROM Control
Reg.
Addr.
(Hex) Bits Name
Description
0xB00 [7:1] Unused
Unused.
0
STATUS_EEPROM
(read only)
This read-only register indicates the status of the data transfer between the EEPROM and the buffer register
bank during the writing and reading of the EEPROM. This signal is also available at the STATUS pin when
Register 0x01D[7] is set.
0: data transfer is complete.
1: data transfer is not complete.
0xB01 [7:1] Unused
Unused.
0
EEPROM
data error
(read only)
This read-only register indicates an error during the data transfer between the EEPROM and the buffer.
0: no error. Data is correct.
1: incorrect data detected.
0xB02 [7:1] Unused
Unused.
1
SOFT_EEPROM
When the EEPROM pin is tied low, setting SOFT_EEPROM resets the AD9520 using the settings saved in the
EEPROM.
1: soft reset with EEPROM settings (self-clearing).
0
Enable EEPROM
write
Enables the user to write to the EEPROM.
0: EEPROM write protection is enabled. User cannot write to the EEPROM (default).
1: EEPROM write protection is disabled. User can write to the EEPROM. Once an EEPROM save/load transfer is
complete, the user must wait a minimum of 10 s before starting the next EEPROM save/load transfer.
0xB03 [7:1] Unused
Unused.
0
REG2EEPROM
Transfers data from the buffer register to the EEPROM (self-clearing).
1: setting this bit initiates the data transfer from the buffer register to the EEPROM (writing process); it is
reset by the IC master after the data transfer is complete. Once an EEPROM save/load transfer is complete,
the user must wait a minimum of 10 s before starting the next EEPROM save/load transfer.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9521SH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
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