參數(shù)資料
型號(hào)： AD9520-5BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 67/76頁(yè)
文件大小： 0K
描述： IC CLOCK GEN EXT VCO 64LFCSP
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
Data Sheet
AD9520-5
Rev. A | Page 7 of 76
CLOCK INPUTS
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLOCK INPUTS (CLK, CLK)
Differential input
Input Frequency
2.4
GHz
High frequency distribution (VCO divider)
2.0
GHz
Distribution only (VCO divider bypassed); this is the
frequency range supported by the channel divider for all
divide ratios except divide-by-17 and divide-by-3
1.6
GHz
Distribution only (VCO divider bypassed); this is the
frequency range supported by all channel divider ratios
Input Sensitivity, Differential
150
mV p-p
Measured at 2.4 GHz; jitter performance is improved with
slew rates > 1 V/ns ; the input sensitivity is sufficient for
ac-coupled LVDS and LVPECL signals
Input Level, Differential
2
V p-p
Larger voltage swings can turn on the protection diodes
and can degrade jitter performance
Input Common-Mode Voltage, VCM
1.3
1.57
1.8
V
Self-biased; enables ac coupling
Input Common-Mode Range, VCMR
1.3
1.8
V
With 200 mV p-p signal applied; dc-coupled
Input Sensitivity, Single-Ended
150
mV p-p
CLK ac-coupled; CLK ac-bypassed to RF ground
Input Resistance
3.9
4.7
5.7
kΩ
Self-biased
Input Capacitance
2
pF
1
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL CLOCK OUTPUTS
Termination = 50 Ω to VS_DRV 2 V
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5,
OUT6, OUT7, OUT8, OUT9, OUT10,
OUT11
Differential (OUT, OUT)
Output Frequency, Maximum
2400
MHz
Using direct to output (see Figure 17); higher frequencies
are possible, but the resulting amplitude does not meet the
VOD specification; the maximum output frequency is limited
by the maximum frequency at the CLK inputs
Output High Voltage, VOH
VS_DRV
1.07
VS_DRV
0.96
VS_DRV
0.84
V
Output Low Voltage, VOL
VS_DRV
1.95
VS_DRV
1.79
VS_DRV
1.64
V
Output Differential Voltage, VOD
660
820
950
mV
VOH VOL for each leg of a differential pair for default
amplitude setting with the driver not toggling; the peak-to-
peak amplitude measured using a differential probe across
the differential pair with the driver toggling is roughly 2×
these values (see Figure 17 for variation over frequency)
CMOS CLOCK OUTPUTS
OUT0A, OUT0B, OUT1A, OUT1B, OUT2A,
OUT2B, OUT3A, OUT3B, OUT4A, OUT4B,
OUT5A, OUT5B, OUT6A, OUT6B, OUT7A,
OUT7B, OUT8A, OUT8B, OUT9A, OUT9B,
OUT10A, OUT10B, OUT11A, OUT11B
Single-ended; termination = 10 pF
Output Frequency
250
MHz
Output Voltage High, VOH
VS
0.1
V
1 mA load, VS_DRV = 3.3 V/2.5 V
Output Voltage Low, VOL
0.1
V
1 mA load, VS_DRV = 3.3 V/2.5 V
Output Voltage High, VOH
2.7
V
10 mA load, VS_DRV = 3.3 V
Output Voltage Low, VOL
0.5
V
10 mA load, VS_DRV = 3.3 V
Output Voltage High, VOH
1.8
V
10 mA load, VS_DRV = 2.5 V
Output Voltage Low, VOL
0.6
V
10 mA load, VS_DRV = 2.5 V
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