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參數(shù)資料
| 型號： | AD9520-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN EXT VCO 64LFCSP |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標準包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD9520-5
Rev. A | Page 35 of 76
means that the charge pump stays in a high impedance state if
no reference clock is present.
The B counter (in the N divider) is reset synchronously with the
charge pump, leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close, resulting in a smaller phase difference for the loop to
settle out.
When using this mode, set the channel dividers to ignore
the SYNC pin (at least after an initial SYNC event). If the dividers
are not set to ignore the SYNC pin, the distribution outputs
turn off when SYNC is taken low to put the part into holdover
mode. The channel divider ignore SYNC function is
programmed in Bit 6 of Register 0x191, Register 0x194, Register
0x197, and Register 0x19A for Channel Divider 0, Channel
Divider 1, Channel Divider 2, and Channel Divider 3, respectively.
Automatic/Internal Holdover Mode
When enabled, this function automatically places the charge
pump into a high impedance state when the loop loses lock.
The assumption is that the only reason the loop loses lock is due
to the PLL losing the reference clock; therefore, the holdover
function puts the charge pump into a high impedance state to
maintain the VCO frequency as close as possible to the original
frequency before the reference clock disappeared.
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD mode. The LD comparator
can be disabled (Register 0x01D[3]), which causes the holdover
function to always sense LD as being high. If DLD is used, it is
possible for the DLD signal to chatter while the PLL is reacquiring
lock. The holdover function may retrigger, thereby preventing
the holdover mode from terminating. Use of the current source
lock detect mode is recommended to avoid this situation (see the
When in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N divider)
is reset synchronously with the charge pump leaving the high
impedance state on the reference path PFD event. This helps
align the edges out of the R and N dividers for faster settling of
the PLL and reduces frequency errors during settling. Because
the prescaler is not reset, this feature works best when the B
and R numbers are close because this results in a smaller phase
difference for the loop to settle out.
After leaving holdover, the loop then reacquires lock, and the
LD pin must go high (if Register 0x01D[3] = 1b) before it can
reenter holdover (CP high impedance).
The holdover function always responds to the state of the currently
selected reference (Register 0x01C). If the loop loses lock
during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
A flowchart of the automatic/internal holdover function
operation is shown in Figure 35.
Figure 35. Flowchart of Automatic/Internal Holdover Mode
NO
YES
PLL ENABLED
DLD == LOW
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
HIGH IMPEDANCE
CHARGE PUMP
REFERENCE
EDGE AT PFD?
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
DLD == HIGH
YES
07239-
069
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK, AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
REG 0x01D[3]: LD PIN COMPARATOR ENABLE.
0b = DISABLE; 1b = ENABLE. WHEN DISABLED,
THE HOLDOVER FUNCTION ALWAYS SENSES
THE LD PIN AS HIGH.
CHARGE PUMP IS MADE HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
CHARGE PUMP REMAINS HIGH IMPEDANCE
UNTIL THE REFERENCE RETURNS.
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN NOW RESETTLE.
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF
THE DLD DELAY COUNTER) WITH THE
REFERENCE AND FEEDBACK CLOCKS
INSIDE THE LOCK WINDOW AT THE PFD.
THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE
AND LOCK BEFORE THE HOLDOVER
FUNCTION CAN BE RETRIGGERED.
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