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參數(shù)資料
| 型號(hào)： | AD9520-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN EXT VCO 64LFCSP |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD9520-5
Rev. A | Page 31 of 76
PLL External Loop Filter
An example of an external loop filter for the PLL is shown in
Figure 30. The external loop filter should be referenced to ground.
A loop filter must be calculated for each desired PLL configuration.
The component values depend upon the VCO frequency, the KVCO,
the PFD frequency, the CP current, the desired loop bandwidth,
and the desired phase margin. The loop filter affects the phase
noise, loop settling time, and loop stability. A knowledge of PLL
theory is necessary for understanding loop filter design. Available
tools, such as ADIsimCLK, can help with the calculation of a loop
filter according to the application requirements.
Figure 30. Example of External Loop Filter for PLL
PLL Reference Inputs
The AD9520 features a flexible PLL reference input circuit that
allows a fully differential input, two separate single-ended inputs,
or a 16.67 MHz to 33.33 MHz crystal oscillator with an on-chip
maintaining amplifier. An optional reference clock doubler
can be used to double the PLL reference frequency. The input
frequency range for the reference inputs is specified in Table 2.
Both the differential and the single-ended inputs are self-biased,
allowing for easy ac coupling of input signals.
Either a differential or a single-ended reference must be specifically
enabled. All PLL reference inputs are off by default.
The differential input and the single-ended inputs share two pins,
REFIN and REFIN (REF1 and REF2, respectively). The desired
reference input type is selected and controlled by Register 0x01C
(see Table 44 and Table 48).
When the differential reference input is selected, the self-bias
level of the two sides is offset slightly (~100 mV, see Table 2) to
prevent chattering of the input buffer when the reference is slow
or missing. This increases the voltage swing that is required of
the driver and overcomes the offset. The differential reference
input can be driven by either ac-coupled LVDS or ac-coupled
LVPECL signals.
The single-ended inputs can be driven by either a dc-coupled
CMOS level signal or an ac-coupled sine wave or square wave. To
avoid input buffer chatter when a single-ended, ac-coupled input
signal stops toggling, the user can set Register 0x018[7] to 1b. This
shifts the dc offset bias point down 140 mV. To increase isolation
and reduce power, each single-ended input can be independently
powered down.
The differential reference input receiver is powered down when
the differential reference input is not selected or when the PLL
is powered down. The single-ended buffers power down when
the PLL is powered down or when their respective individual
power-down registers are set. When the differential mode is
selected, the single-ended inputs are powered down.
In differential mode, the reference input pins are internally self-
biased so that they can be ac-coupled via capacitors. It is possible to
dc couple to these inputs. If the differential REFIN is driven by
a single-ended signal, the unused side (REFIN) should be
decoupled via a suitable capacitor to a quiet ground. Figure 31
shows the equivalent circuit of REFIN.
Figure 31. REFIN Equivalent Circuit for Non-XTAL Mode
Crystal mode is nearly identical to differential mode. The user
enables a maintaining amplifier by setting the enable XTAL
OSC bit, and putting a series resonant, AT fundamental cut
crystal across the REFIN and REFIN pins.
Reference Switchover
The AD9520 supports dual single-ended CMOS inputs, as well
as a single differential reference input. In the dual single-ended
reference mode, the AD9520 supports automatic revertive and
manual PLL reference clock switching between REF1 (on Pin
REFIN) and REF2 (on Pin REFIN). This feature supports
networking and other applications that require smooth switching
of redundant references. When used in conjunction with the
automatic holdover function, the AD9520 can achieve a worst-
case reference input switchover with an output frequency
disturbance as low as 10 ppm.
CLK/CLK
EXTERNAL
VCO/VCXO
CHARGE
PUMP
CP
C1
C2
C3
R1
R2
AD9520-5
072
39-
143
VS
REF1
REF2
REFIN
150
10k
12k
10k
REFIN
85k
VS
85k
VS
07
23
9-
0
66
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