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參數(shù)資料
| 型號(hào)： | AD9520-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 64/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN EXT VCO 64LFCSP |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD9520-5
Rev. A | Page 67 of 76
Reg.
Addr.
(Hex) Bits
Name
Description
0x195 [7:3]
Unused
Unused.
2
Channel 1 power-down
Channel 1 powers down.
0: normal operation (default).
1: powered down. (Setting this bit puts OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 into safe
power-down mode.)
1
Channel 1 direct-to-output
Connects OUT3, OUT4, and OUT5 to Divider 1 or directly to CLK.
0: OUT3, OUT4, and OUT5 are connected to Divider 1 (default).
1: If Register 0x1E1[0] = 0b, the CLK is routed directly to OUT3, OUT4, and OUT5.
If Register 0x1E1[0] = 1b, there is no effect.
0
Disable Divider 1 DCC
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x196 [7:4]
Divider 2 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays low.
A value of 0x1 means that the divider is low for two input clock cycles (default: 0x1).
[3:0]
Divider 2 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays high.
A value of 0x1 means that the divider is high for two input clock cycles (default: 0x1).
0x197 7
Divider 2 bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6
Divider 2 ignore SYNC
Ignores SYNC.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 2 force high
Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that
this bit has no effect if the channel divider is bypassed, but the driver polarity can still be reversed.
0: divider output is forced to low (default).
1: divider output is forced to the setting stored in Bit 4 of this register.
4
Divider 2 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 2 phase offset
Phase offset(default: 0x0).
0x198 [7:3]
Unused
Unused.
2
Channel 2 power-down
Channel 2 powers down.
0: normal operation (default).
1: powered down. (Setting this bit puts OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 into safe
power-down mode.)
1
Channel 2 direct-to-output
Connects OUT6, OUT7, and OUT8 to Divider 2 or directly to CLK.
0: OUT6, OUT7, and OUT8 are connected to Divider 2 (default).
1: If Register 0x1E1[0] = 0b, the CLK is routed directly to OUT6, OUT7, and OUT8.
If Register 0x1E1[0] = 1b, there is no effect.
0
Disable Divider 2 DCC
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x199 [7:4]
Divider 3 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default: 0x0).
[3:0]
Divider 3 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default: 0x0).
0x19A 7
Divider 3 bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6
Divider 3 ignore SYNC
Ignores SYNC.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
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| AD9521JH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
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| AD9521SH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
| AD9521TE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
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