參數(shù)資料
型號(hào)： AD9520-5BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 35/76頁
文件大小： 0K
描述： IC CLOCK GEN EXT VCO 64LFCSP
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD9520-5
Data Sheet
Rev. A | Page 40 of 76
Duty-cycle correction requires the following channel divider
conditions:
An even division must be set as M = N.
An odd division must be set as M = N + 1.
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2), expressed as a percent.
Table 30 to Table 33 show the output duty cycle for various
configurations of the channel divider and VCO divider.
Table 30. Channel Divider Output Duty Cycle with VCO Divider ≠ 1; Input Duty Cycle Is 50%
VCO Divider
DX
Output Duty Cycle
N + M + 2
Disable Divider x DCC = 1b
Disable Divider x DCC = 0b
Even
Channel divider bypassed
50%
Odd = 3
Channel divider bypassed
33.3%
50%
Odd = 5
Channel divider bypassed
40%
50%
Even, odd
Even
(N + 1)/(N + M + 2)
50%, requires M = N
Even, odd
Odd
(N + 1)/(N + M + 2)
50%, requires M = N + 1
Table 31. Channel Divider Output Duty Cycle with VCO Divider ≠ 1; Input Duty Cycle Is X%
VCO Divider
DX
Output Duty Cycle
N + M + 2
Disable Divider x DCC = 1b
Disable Divider x DCC = 0b
Even
Channel divider bypassed
50%
Odd = 3
Channel divider bypassed
33.3%
(1 + X%)/3
Odd = 5
Channel divider bypassed
40%
(2 + X%)/5
Even
(N + 1)/(N + M + 2)
50%, requires M = N
Even
Odd
(N + 1)/(N + M + 2)
50%, requires M = N + 1
Odd = 3
Even
(N + 1)/(N + M + 2)
50%, requires M = N
Odd = 3
Odd
(N + 1)/(N + M + 2)
(3N + 4 + X%)/(6N + 9), requires M = N + 1
Odd = 5
Even
(N + 1)/(N + M + 2)
50%, requires M = N
Odd = 5
Odd
(N + 1)/(N + M + 2)
(5N + 7 + X%)/(10N + 15), requires M = N + 1
Table 32. Channel Divider Output Duty Cycle When the VCO Divider Is Enabled and Set to 1
Input Clock
Duty Cycle
DX
Output Duty Cycle
N + M + 2
Disable Divider x DCC = 1b
Disable Divider x DCC = 0b
Any
Even
(N + 1)/(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/(M + N + 2)
50%, requires M = N + 1
X%
Odd
(N + 1)/(M + N + 2)
(N + 1 + X%)/(2 × N + 3), requires M = N + 1
The channel divider must be enabled when the VCO divider = 1.
Table 33. Channel Divider Output Duty Cycle When the VCO Divider Is Bypassed
Input Clock
Duty Cycle
DX
Output Duty Cycle
N + M + 2
Disable Divider x DCC = 1b
Disable Divider x DCC = 0b
Any
Channel divider bypassed
Same as input duty cycle
Any
Even
(N + 1)/(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/(M + N + 2)
50%, requires M = N + 1
X%
Odd
(N + 1)/(M + N + 2)
(N + 1 + X%)/(2 × N + 3), requires M = N + 1
If the CLK input is routed directly to the output, the duty cycle of the output is the same as the CLK input.
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