參數(shù)資料
型號(hào)： AD9520-5BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/76頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN EXT VCO 64LFCSP
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
Data Sheet
AD9520-5
Rev. A | Page 41 of 76
Phase Offset or Coarse Time Delay
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 34).
These settings determine the number of cycles (successive rising
edges) of the channel divider input frequency by which to offset, or
delay, the rising edge of the output of the divider. This delay is
with respect to a nondelayed output (that is, with a phase offset
of zero). The amount of the delay is set by five bits loaded into
the phase offset (PO) register plus the start high (SH) bit for
each channel divider. When the start high bit is set, the delay is
also affected by the number of low cycles (M) programmed for
the divider.
The SYNC function must be used to make phase offsets effective
Table 34. Setting Phase Offset and Division
Divider
Start
High
(SH) Bits
Phase
Offset
(PO) Bits
Low Cycles,
M Value Bits
High Cycles,
N Value Bits
0
0x191[4]
0x191[3:0]
0x190[7:4]
0x190[3:0]
1
0x194[4]
0x194[3:0]
0x193[7:4]
0x193[3:0]
2
0x197[4]
0x197[3:0]
0x196[7:4]
0x196[3:0]
3
0x19A[4]
0x19A[3:0]
0x199[7:4]
0x199[3:0]
Note that the value stored in the register equals the number of
cycles minus one. For example, Register 0x190[7:4] = 0001b
equals two low cycles (M = 2) for Divider 0.
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to DX).
TX = period of the clock signal at the input of the divider, DX
(in seconds).
Φ =
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0].
The channel divide by is set as N = high cycles and M = low
cycles.
Case 1
For Φ ≤ 15,
Δt = Φ × TX
Δc = Δt/TX = Φ
Case 2
For Φ ≥ 16,
Δt = (Φ 16 + M + 1) × TX
Δc = Δt/TX
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input clock
cycle. Figure 39 shows the results of setting such a coarse offset
between outputs.
Figure 39. Effect of Coarse Phase Offset (or Delay)
Synchronizing the Outputs—SYNC Function
The AD9520 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions. These conditions include the
divider ratio and phase offsets for a given channel divider. This
allows the user to specify different divide ratios and phase offsets
for each of the four channel dividers. Releasing the SYNC pin
allows the outputs to continue clocking with the preset conditions
applied.
Synchronization of the outputs is executed in the following ways:
The SYNC pin is forced low and then released (manual sync).
By setting and then resetting any one of the following three
bits: the soft SYNC bit (Register 0x230[0]), the soft reset bit
(Register 0x000[5] [mirrored]), and the power-down
distribution reference bit (Register 0x230[1]).
Synchronization of the outputs can be executed as part of
the chip power-up sequence.
The RESET pin is forced low and then released (chip reset).
The PD pin is forced low, then released (chip power-down).
The most common way to execute the SYNC function is to use
the SYNC pin to perform a manual synchronization of the outputs.
This requires a low going signal on the SYNC pin, which is held
low and then released when synchronization is desired.
The timing of the SYNC operation is shown in Figure 40 (using
the VCO divider) and in Figure 41 (the VCO divider is not
used). There is an uncertainty of up to one cycle of the clock at the
input to the channel divider due to the asynchronous nature of the
SYNC signal with respect to the clock edges inside the AD9520.
The pipeline delay from the SYNC rising edge to the beginning
of the synchronized output clocking is between 14 cycles and
15 cycles of clock at the channel divider input, plus either one
cycle of the VCO divider input (see Figure 40) or one cycle of
the channel divider input (see Figure 41), depending on whether
the VCO divider is used. Cycles are counted from the rising
edge of the signal. In addition, there is an additional 1.2 ns (typical)
delay from the SYNC signal to the internal synchronization logic,
as well as the propagation delay of the output driver. The driver
propagation delay is approximately 100 ps for the LVPECL
driver and approximately 1.5 ns for the CMOS driver.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Tx
DIVIDER 0
DIVIDER 1
DIVIDER 2
CHANNEL
DIVIDER INPUT
SH = 0
PO = 0
SH = 0
PO = 1
SH = 0
PO = 2
1 × Tx
2 × Tx
CHANNEL DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
07239-
071
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