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參數(shù)資料
| 型號： | AD9520-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 61/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN EXT VCO 64LFCSP |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9520-5
Data Sheet
Rev. A | Page 64 of 76
Reg.
Addr.
(Hex)
Bits Name
Description
0x01D 7
Enable
STATUS_
EEPROM at
STATUS pin
Enables the STATUS_EEPROM signal at the STATUS pin.
0: the STATUS pin is controlled by the Register 0x017[7:2] selection.
1: selects the STATUS_EEPROM signal at the STATUS pin. This bit overrides the Reigster 0x017[7:2] selection (default).
6
Enable
XTAL OSC
Enables the maintaining amplifier needed by a crystal oscillator at the PLL reference input.
0: crystal oscillator maintaining amplifier disabled (default).
1: crystal oscillator maintaining amplifier enabled.
5
Enable clock
doubler
Enables PLL reference input clock doubler.
0: doubler disabled (default).
1: doubler enabled.
4
Disable PLL
status
register
Disables the PLL status register readback.
0: PLL status register enabled (default).
1: PLL status register disabled. If this bit is set, Register 0x01F is not automatically updated.
3
Enable
LD pin
comparator
Enables the LD pin voltage comparator. Used with the LD pin current source lock detect mode. When the AD9520 is in internal
(automatic) holdover mode, this bit enables the use of the voltage on the LD pin to determine if the PLL was previously in a
locked state (see Figure 35). Otherwise, this can be used with the REFMON and STATUS pins to monitor the voltage on the LD pin.
0: disables LD pin comparator and ignores the LD pin voltage; internal/automatic holdover controller treats this pin as true (high, default).
1: enables LD pin comparator (uses LD pin voltage to determine if the PLL was previously locked).
2
Unused
Unused.
1
Enable
external
holdover
Enables the external hold control through the SYNC pin. (This bit disables the internal holdover mode.)
0: automatic holdover mode; holdover controlled by the automatic holdover circuit (default).
1: external holdover mode; holdover controlled by the SYNC pin.
0
Enable
holdover
Enables the internally controlled holdover function.
0: holdover disabled (default).
1: holdover enabled.
0x01E [7:2] Unused
Unused.
1
Enable zero
delay
Enables zero delay function.
0: disables zero delay function (default).
1: enables zero delay function.
0
Unused
Unused.
0x01F [7:6] Unused
Unused.
5
Holdover
active
(read only)
Readback register. Indicates if the part is in the holdover state (see Figure 35). Note that this is not the same as holdover enabled.
0: not in holdover state.
1: holdover state active.
4
REF2
selected
(read only)
Readback register. Indicates which PLL reference is selected as the input to the PLL.
0: REF1 selected (or differential reference if in differential mode).
1: REF2 selected.
3
CLK
frequency >
threshold
(read only)
Readback register. Indicates if the external CLK input frequency is greater than the threshold (see Table 14: REF1, REF2, and
external CLK frequency status monitor parameter).
0: the external CLK frequency is less than the threshold.
1: the external CLK frequency is greater than the threshold.
2
REF2
frequency >
threshold
(read only)
Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by Register 0x01A[6].
0: REF2 frequency is less than the threshold frequency.
1: REF2 frequency is greater than the threshold frequency.
1
REF1
frequency >
threshold
(read only)
Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency set by Register 0x01A[6].
0: REF1 frequency is less than the threshold frequency.
1: REF1 frequency is greater than the threshold frequency.
0
Digital lock
detect
(read only)
Readback register. Digital lock detect.
0: PLL is not locked.
1: PLL is locked.
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| AD9521SH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Log/Antilog Amplifier |
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