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參數(shù)資料
| 型號(hào)： | AD9520-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 65/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN EXT VCO 64LFCSP |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9520-5
Data Sheet
Rev. A | Page 68 of 76
Reg.
Addr.
(Hex) Bits
Name
Description
5
Divider 3 force high
Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that
this bit has no effect if the channel divider is bypassed, but the driver polarity can still be reversed.
0: divider output is forced to low (default).
1: divider output is forced to the setting stored in Bit 4 of this register.
4
Divider 3 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 3 phase offset
Phase offset (default: 0x0).
0x19B [7:3]
Unused
Unused.
2
Channel 3 power-down
Channel 3 powers down.
0: normal operation (default).
1: powered down. (Setting this bit puts OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 into
safe power-down mode.)
1
Channel 3 direct-to-output
Connects OUT9, OUT10, and OUT11 to Divider 3 or directly to CLK.
0: OUT9, OUT10, and OUT11 are connected to Divider 3 (default).
1: If Register 0x1E1[0] = 0b, the CLK is routed directly to OUT9, OUT10, and OUT11.
If Register 0x1E1[0] = 1b, there is no effect.
0
Disable Divider 3 DCC
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Table 51. VCO Divider and CLK Input
Reg.
Addr.
(Hex) Bits
Name
Description
0x1E0 [7:3]
Unused
Unused.
[2:0]
VCO divider
Bit 2
Bit 1
Bit 0
Divide
0
2 (default)
0
1
3
0
1
0
4
0
1
5
1
0
6
1
0
1
Output static
1
0
1 (bypass)
1
Output static
0x1E1 [7:5]
Unused
Unused.
4
Power down clock input
section
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
0
Bypass VCO divider
Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider.
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