參數(shù)資料
型號： AD9520-5BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 55/76頁
文件大?。?/td> 0K
描述： IC CLOCK GEN EXT VCO 64LFCSP
設(shè)計資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 750
類型： 時鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
Data Sheet
AD9520-5
Rev. A | Page 59 of 76
Table 48. PLL
Reg.
Addr.
(Hex)
Bits
Name
Description
0x010
7
PFD polarity
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO.
0: positive (higher control voltage produces higher frequency) (default).
1: negative (higher control voltage produces lower frequency).
[6:4] CP current
Charge pump current (with CPRSET = 5.1 kΩ).
Bit
6
Bit
5
Bit
4
ICP (mA)
0
0.6
0
1
1.2
0
1
0
1.8
0
1
2.4
1
0
3.0
1
0
1
3.6
1
0
4.2
1
4.8 (default)
[3:2] CP mode
Charge pump operating mode.
Bit
3
Bit
2
Charge Pump Mode
0
High impedance state.
0
1
Forces source current (pump-up).
1
0
Forces sink current (pump-down).
1
Normal operation (default).
[1:0] PLL power-
down
PLL operating mode.
Bit
1
Bit
0
Mode
0
Normal operation; this mode must be selected to use the PLL.
0
1
Asynchronous power-down (default).
1
0
Unused.
1
Synchronous power-down.
0x011
[7:0] 14-bit R counter,
Bits[7:0] (LSB)
Reference divider LSBs—lower eight bits. The reference divider (also called the R divider or R counter) is
14 bits long. The lower eight bits are in this register (default: 0x01).
0x012
[7:6] Unused
Unused.
[5:0] 14-bit R counter,
Bits[13:8] (MSB)
Reference divider MSBs—upper six bits. The reference divider (also called the R divider or R counter) is
14 bits long. The upper six bits are in this register (default: 0x00).
0x013
[7:6] Unused
Unused.
[5:0] 6-bit A counter
A counter (part of N divider). The N divider is also called the feedback divider (default: 0x00).
0x014
[7:0] 13-bit B counter,
Bits[7:0] (LSB)
B counter (part of N divider)—lower eight bits. The N divider is also called the feedback divider (default: 0x03).
0x015
[7:5] Unused
Unused.
[4:0] 13-bit B counter,
Bits[12:8] (MSB)
B counter (part of N divider)—upper five bits. The N divider is also called the feedback divider (default: 0x00).
0x016
7
Set CP pin
to VCP/2
Sets the CP pin to one-half of the VCP supply voltage.
0: CP normal operation (default).
1: CP pin set to VCP/2.
6
Reset R counter Resets R counter (R divider).
0: normal (default).
1: holds R counter in reset.
5
Reset A and B
counters
Resets A and B counters (part of N divider).
0: normal (default).
1: holds A and B counters in reset.
4
Reset all
counters
Resets R, A, and B counters.
0: normal (default).
1: holds R, A, and B counters in reset.
3
B counter
bypass
B counter bypass. This is valid only when operating the prescaler in FD mode.
0: normal (default).
1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for
the N divider.
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