參數(shù)資料
型號： AD9520-5BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 56/76頁
文件大?。?/td> 0K
描述： IC CLOCK GEN EXT VCO 64LFCSP
設(shè)計資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 750
類型： 時鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:12，2:24
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD9520-5
Data Sheet
Rev. A | Page 6 of 76
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE OFFSET IN ZERO DELAY
REF refers to REFIN (REF1)/REFIN (REF2)
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Zero Delay Mode
560
1060
1310
ps
When N delay and R delay are bypassed
Phase Offset (REF-to-LVPECL Clock Output
Pins) in Zero Delay Mode
320
+50
+240
ps
When N delay setting = 110b, and R delay is bypassed
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge Pump/
Phase Frequency Detector2
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output
of the VCO and subtracting 20 log(N) (where N is
the value of the N divider)
500 kHz PFD Frequency
165
dBc/Hz
1 MHz PFD Frequency
162
dBc/Hz
10 MHz PFD Frequency
152
dBc/Hz
50 MHz PFD Frequency
144
dBc/Hz
PLL Figure of Merit (FOM)
222
dBc/Hz
Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is
an approximation of the PFD/CP in-band phase
noise (in the flat region) inside the PLL loop
bandwidth; when running closed-loop, the phase
noise, as observed at the VCO output, is increased
by 20 log(N); PLL figure of merit decreases with
decreasing slew rate; see Figure 11
PLL DIGITAL LOCK DETECT WINDOW3
Signal available at the LD, STATUS, and REFMON
pins when selected by appropriate register
settings; the lock detect threshold varies linearly
with the value of the CPRSET resistor
Lock Threshold (Coincidence of Edges)
Selected by Register 0x017[1:0] and Register
0x018[4] (this is the threshold to go from unlock to
lock)
Low Range (ABP 1.3 ns, 2.9 ns)
3.5
ns
Register 0x017[1:0] = 00b, 01b,11b;
Register 0x018[4] = 1b
High Range (ABP 1.3 ns, 2.9 ns)
7.5
ns
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 0b
High Range (ABP 6.0 ns)
3.5
ns
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
Unlock Threshold (Hysteresis)3
Selected by Register 0x017[1:0] and Register
0x018[4] (this is the threshold to go from lock to
unlock)
Low Range (ABP 1.3 ns, 2.9 ns)
7
ns
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 1b
High Range (ABP 1.3 ns, 2.9 ns)
15
ns
Register 0x017[1:0] = 00b, 01b, 11b;
Register 0x018[4] = 0b
High Range (ABP 6.0 ns)
11
ns
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
1
The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
2
In-band means within the LBW of the PLL.
3
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
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