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參數(shù)資料
| 型號： | AD9520-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN EXT VCO 64LFCSP |
| 設(shè)計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12，2:24 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD9520-5
Rev. A | Page 45 of 76
SERIAL CONTROL PORT
The AD9520 serial control port is a flexible, synchronous serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9520 serial control port is compatible with most synchronous
transfer formats, including Philips IC, Motorola SPI, and
Intel SSR protocols. The AD9520 IC implementation deviates
from the classic IC specification on two specifications, and
these deviations are documented in Table 11 of this data sheet.
The serial control port allows read/write access to all registers
that configure the AD9520.
SPI/IC PORT SELECTION
The AD9520 has two serial interfaces, SPI and IC. Users can
select either SPI or IC depending on the states of the three level
(high, open, low) logic input pins, SP1 and SP0. When both SP1
and SP0 are high, the SPI interface is active. Otherwise, IC is active
with eight different IC slave address (seven bits wide) settings
(see Table 35). The four MSBs of the slave address are hardware
coded as 1011b; the three LSBs are programmed by SP1 and SP0.
Table 35. Serial Port Mode Selection
SP1
SP0
Address
Low
IC, 1011000b
Low
Open
IC, 1011001b
Low
High
IC, 1011010b
Open
Low
IC, 1011011b
Open
IC, 1011100b
Open
High
IC, 1011101b
High
Low
IC, 1011110b
High
Open
IC, 1011111b
High
SPI
IC SERIAL PORT OPERATION
The AD9520 IC port is based on the IC fast mode standard.
The AD9520 supports both IC protocols: standard mode
(100 kHz) and fast mode (400 kHz).
The AD9520 IC port has a 2-wire interface consisting of a serial
data line (SDA) and a serial clock line (SCL). In an IC bus system,
the AD9520 is connected to the serial bus (data bus SDA and clock
bus SCL) as a slave device, meaning that no clock is generated by
the AD9520. The AD9520 uses direct 16-bit (two bytes) memory
addressing instead of traditional 8-bit (one byte) memory
addressing.
I2C Bus Characteristics
Table 36. I2C Bus Definitions
Abbreviation
Definition
S
Start
Sr
Repeated start
P
Stop
A
Acknowledge
A
No acknowledge
W
Write
R
Read
One pulse on the SCL clock line is generated for each data bit
transferred.
The data on the SDA line must not change during the high
period of the clock. The state of the data line can change only when
the clock on the SCL line is low.
Figure 44. Valid Bit Transfer
A start condition is a transition from high to low on the SDA
line while SCL is high. The start condition is always generated
by the master to initialize the data transfer.
A stop condition is a transition from low to high on the SDA
line while SCL is high. The stop condition is always generated
by the master to end the data transfer.
Figure 45. Start and Stop Conditions
A byte on the SDA line is always eight bits long. An acknowledge
bit must follow every byte. Bytes are sent MSB first.
The acknowledge bit is the ninth bit attached to any 8-bit data
byte. An acknowledge bit is always generated by the receiving
device (receiver) to inform the transmitter that the byte has
been received. It is accomplished by pulling the SDA line low
during the ninth clock pulse after each 8-bit data byte.
The no acknowledge bit is the ninth bit attached to any 8-bit
data byte. A no acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has not been received. It is accomplished by leaving the SDA
line high during the ninth clock pulse after each 8-bit data byte.
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
07239-
160
START
CONDITION
S
STOP
CONDITION
P
SDA
SCL
07239-
161
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