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| 型號： | AD7294BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT I2C/SRL 1M 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 22.22k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 4.4 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
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Data Sheet
AD7294
Rev. H | Page 41 of 48
ALERTS AND LIMITS THEORY
ALERT_FLAG BIT
The alert_flag bit indicates whether the conversion result being
read or any other channel result has violated the limit registers
associated with it. If an alert occurs and the alert_flag bit is set,
the master can read the alert status register to obtain more
information on where the alert occurred.
ALERT STATUS REGISTERS
The alert status registers are 8-bit read/write registers that provide
information on an alert event. If a conversion results in activa-
tion of the ALERT/BUSY pin or the alert_flag bit in the result
register or TSENSE registers, the alert status register can be read to
get more information (see Figure 57 for the alert register
structure).
05747-
057
ALERT
REGISTER
A
ALERT
REGISTER
B
ALERT
REGISTER
C
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
VIN3 HIGH ALERT
VIN3 LOW ALERT
VIN2 HIGH ALERT
VIN2 LOW ALERT
VIN1 HIGH ALERT
VIN1 LOW ALERT
VIN0 HIGH ALERT
VIN0 LOW ALERT
RESERVED
ISENSE2 OVERRANGE*
ISENSE2 HIGH ALERT
ISENSE1 OVERRANGE*
ISENSE2 LOW ALERT
ISENSE1 LOW ALERT
ISENSE1 HIGH ALERT
OPEN DIODE FLAG*
OVER TEMP ALERT*
TSENSEINT HIGH ALERT
TSENSE2 HIGH ALERT
TSENSEINT LOW ALERT
TSENSE2 LOW ALERT
TSENSE1 LOW ALERT
TSENSE1 HIGH ALERT
ALERT
FLAG
OR
ALERT/BUSY
CONFIGURATION
REGISTER
D2 = 1, D1 = 0
* THESE BITS ARE ALWAYS ACTIVE, ALL OTHER BITS CAN BE
PROGRAMMED TO BE ACTIVE OR NOT AS REQUIRED.
Figure 57. Alert Register Structure
Register A (see Table 19) consists of four channels with two status
bits per channel, one corresponding to each of the DATAHIGH and
DATALOW limits. It stores the alert event data for VIN3 to VIN0,
which are the standard voltage inputs. When the content of this
register is read, any bit with a status of 1 indicates a violation of
its associated limit; that is, it identifies the channel and whether
the violation occurred on the upper or lower limit. If a second
alert event occurs on another channel before the content of the
alert register has been read, the bit corresponding to the second
alert event is also set.
Register B (see Table 20) consists of three channels also with
two status bits per channel, representing the specified DATAHIGH
and DATALOW limits. Bits[D3:D0] correspond to the high and low
limit alerts for the current sense inputs. Bit D4 and Bit D5 represent
the ISENSE1 OVERRANGE and ISENSE2 OVERRANGE of VREF/10.41.
During power-up, it is possible for the fault outputs to be trig-
gered, depending on which supply comes up first. Clearing these
bits as part of the initialization routine is recommended on
power-up by writing a 1 to both D4 and D5.
Internal circuitry in the AD7294 can alert if either the D1± or
the D2± input pins for the external temperature sensor are open
circuit. The most significant bit of Register C (see Table 21)
alerts the user when an open diode flag occurs on the external
temperature sensors. If the internal temperature sensor detects
an AD7294 die temperature greater than 150°C, the overtem-
perature alert bit, Bit D6 in Register C, is set and the DAC
outputs are set to a high impedance sate. The remaining six
bits in Register 6 store alert event data for TSENSE1, TSENSE2, and
TSENSEINT with two status bits per channel, one corresponding to
each of the DATAHIGH and DATALOW limits.
To clear the full content of any one of the alert registers, write a
code of FF (all ones) to the relevant registers. Alternatively, the
user can write to the respective alert bit in the selected alert
register to clear the alert associated with that bit. The entire
contents of all the alert status registers can be cleared by writing
a 1 to Bit D1 and Bit D2 in the configuration register, as shown
in Table 24. However, this operation then enables the ALERT/
BUSY pin for subsequent conversions.
DATAHIGH AND DATALOW MONITORING FEATURES
The AD7294 signals an alert (in either hardware via the
ALERT/BUSY pin, software via the alert_flag bit, or both,
depending on the configuration) if the result moves outside the
upper or lower limit set by the user.
The DATAHIGH register stores the upper limit that activates the
ALERT/BUSY output pin and/or the alert_flag bit in the conver-
sion result register. If the conversion result is greater than the value
in the DATAHIGH register, an alert occurs. The DATALOW register
stores the lower limit that activates the ALERT/BUSY output pin
and/or the alert_flag bit in the conversion result register. If the
conversion result is less than the value in the DATALOW register,
an alert occurs.
An alert associated with either the DATAHIGH or DATALOW
register is cleared automatically once the monitored signal is
back in range; that is, the conversion result is between the limits.
The content of the alert register is updated after each conversion.
A conversion is performed every 50 s in autocycle mode,
so the content of the alert register may change every 50 s. If
the ALERT pin signals an alert event and the content of the alert
register is not read before the next conversion is complete, the
content of the register may be changed if the signal being
monitored returns between the prespecified limits. In these circum-
stances, the ALERT pin no longer signals the occurrence of an
alert event.
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