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| 型號： | AD7294BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT I2C/SRL 1M 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 22.22k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 4.4 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
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Data Sheet
AD7294
Rev. H | Page 21 of 48
signal so that it is correctly formatted for the ADC. Figure 37
shows a typical connection diagram when operating the ADC
in single-ended mode.
VIN
0V
+1.25V
–1.25V
REFOUT ADC
VIN0
AD7294
1
VIN3
R
3R
R
0V
+2.5V
0.47F
1ADDITIONAL PINS OMITTED FOR CLARITY.
05747-
018
Figure 37. Single-Ended Mode Connection Diagram
Differential Mode
The AD7294 can have two differential analog input pairs.
Differential signals have some benefits over single-ended
signals, including noise immunity based on the common-
mode rejection of the device and improvements in distortion
performance. Figure 38 defines the fully differential analog
input of the AD7294.
VIN+
AD7294
1
VIN–
VREF p-p
COMMON-MODE
VOLTAGE
1ADDITIONAL PINS OMITTED FOR CLARITY.
05747-
019
Figure 38. Differential Input Definition
The amplitude of the differential signal is the difference
between the signals applied to VIN+ and VIN in each differential
pair (VIN+ VIN). The resulting converted data is stored in twos
complement format in the result register. Simultaneously drive
VIN0 and VIN1 by two signals, each of amplitude VREF (or 2 ×
VREF, depending on the range chosen), that are 180° out of
phase. Assuming the 0 V to VREF range is selected, the amplitude
of the differential signal is, therefore, VREF to +VREF peak-to-
peak (2 × VREF), regardless of the common mode (VCM).
The common mode is the average of the two signals
(VIN+ + VIN)/2
The common mode is, therefore, the voltage on which the two
inputs are centered.
This results in the span of each input being VCM ± VREF/2. This
voltage has to be set up externally, and its range varies with the
reference value, VREF. As the value of VREF increases, the common-
mode range decreases. When driving the inputs with an amplifier,
the actual common-mode range is determined by the output
voltage swing of the amplifier.
The common mode must be in this range to guarantee the
functionality of the AD7294.
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise-free signal of amplitude VREF to
+VREF, corresponding to the digital output codes of 2048 to
+2047 in twos complement format.
If the 2 × VREF range is used, the input signal amplitude extends
from 2 ×VREF (VIN+ = 0 V, VIN = VREF) to +2 × VREF (VIN = 0 V,
VIN+ = VREF).
Driving Differential Inputs
require that VIN+ and VIN be driven simultaneously with two
equal signals that are 180° out of phase. The common mode on
which the analog input is centered must be set up externally. The
common-mode range is determined by VREF, the power supply,
and the particular amplifier used to drive the analog inputs.
Differential modes of operation with either an ac or dc input
provide the best THD performance over a wide frequency
range. Because not all applications have a signal preconditioned
for differential operation, there is often a need to perform a single-
ended-to-differential conversion.
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential signal
to one of the analog input pairs of the AD7294. The circuit con-
figurations illustrated in Figure 39 show how a dual op amp can
be used to convert a single-ended bipolar signal into a differential
unipolar input signal.
The voltage applied to Point A sets up the common-mode voltage.
As shown in Figure 39, Point A connects to the reference, but any
value in the common-mode range can be the input at Point A to
set up the common mode. The AD8022 is a suitable dual op amp
that can be used in this configuration to provide differential
drive to the AD7294.
Care is required when choosing the op amp because the selection
depends on the required power supply and system performance
objectives. The driver circuits in Figure 39 are optimized for dc
coupling applications requiring best distortion performance.
The differential op amp driver circuit shown in Figure 39 is
configured to convert and level shift a single-ended, ground
referenced (bipolar) signal to a differential signal centered at
the VREF level of the ADC.
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