TSENSE OFFSET REGISTERS (0x26 AND 0x27)" />
參數(shù)資料
型號: AD7294BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 28/49頁
文件大?。?/td> 0K
描述: IC ADC 12BIT I2C/SRL 1M 56LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: ADC,DAC
分辨率(位): 12 b
采樣率(每秒): 22.22k
數(shù)據(jù)接口: I²C,串行
電壓電源: 模擬和數(shù)字
電源電壓: 4.4 V ~ 5.5 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 56-LFCSP-VQ(8x8)
包裝: 托盤
Data Sheet
AD7294
Rev. H | Page 33 of 48
TSENSE OFFSET REGISTERS (0x26 AND 0x27)
The AD7294 has temperature offset, 8-bit twos complement regis-
ters for both Remote Channel TSENSE1 and Remote Channel TSENSE2.
It allows the user to add or subtract an offset to the temperature.
The offset registers for TSENSE1 and TSENSE2 are 8-bit read/write
registers that store data in a twos complement format. This data
is subtracted from the temperature readings taken by TSENSE1
and TSENSE2 temperature sensors. The offset is implemented
before the values are stored in the TSENSE result register.
The offset registers can be used to compensate for transistors
with different ideality factors because the TSENSE results are
based on the 2N3906 transistor ideality factor. Different
transistors with different ideality factors result in different
offsets within the region of interest, which can be compensated
for by using this register.
Table 33. TSENSE Offset Data Format
Input
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
Value (°C)
32
+16
+8
+4
+2
+1
+0.5
+0.25
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