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參數(shù)資料
| 型號(hào)： | AD7294BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/49頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT I2C/SRL 1M 56LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 22.22k |
| 數(shù)據(jù)接口： | I²C，串行 |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 4.4 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
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AD7294
Data Sheet
Rev. H | Page 28 of 48
COMMAND REGISTER (0x00)
Writing in the command register puts the part into command
mode. When in command mode, the part cycles through the
selected channels from LSB (D0) to MSB (D7) on each subse-
quent read (see Table 10). A channel is selected for conversion
if a one is written to the desired bit in the command register. On
power-up, all bits in the command register are set to zero. If the
external TSENSE channels are selected in the command register
byte, it is not actually requesting a conversion. The result of the
last automatic conversion is output as part of the sequence (see
the Modes of Operation section).
If a command mode conversion is required while the autocycle
mode is active, it is necessary to disable the autocycle mode
before proceeding to the command mode (see the Autocycle
Mode section for more details).
RESULT REGISTER (0x01)
The result register is a 16-bit read-only register. The conversion
results for the four uncommitted ADC inputs and the two ISENSE
channels are stored in the result register for reading.
Bit D14 to Bit D12 are the channel allocation bits, each of which
identifies the ADC channel that corresponds to the subsequent
result (see the ADC Channel Allocation section for more
details). Bit D11 to Bit D0 contain the most recent ADC result.
D15 is reserved as an alert_flag bit. Table 11 lists the contents of
the first byte that is read from the AD7294 results register; Table 12
lists the contents of the second byte read.
Table 10. Command Register1
MSB
LSB
Bits
D7
D6
D5
D4
D3
D2
D1
D0
Channel
Read out last
result from
T
SENSE2
Read out last
result from
T
SENSE1
I
SENSE2
I
SENSE1
V
IN3 (S.E.)
or
V
IN3 VIN2
(DIFF)
V
IN2 (S.E.)
or
V
IN2 VIN3
(DIFF)
V
IN1 (S.E.)
or
V
IN1 VIN0
(DIFF)
V
IN0 (S.E.)
or
V
IN0 VIN1
(DIFF)
1 S.E. indicates single-ended and DIFF indicates differential.
Table 11. Result Register (First Read)
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
Alert_Flag
CH
ID2
CH
ID1
CH
ID0
B11
B10
B9
B8
Table 12. Result Register (Second Read)
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
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