DACA,DACB
參數(shù)資料
型號(hào)： AD7294BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 25/49頁
文件大小： 0K
描述： IC ADC 12BIT I2C/SRL 1M 56LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： ADC，DAC
分辨率（位）： 12 b
采樣率（每秒）： 22.22k
數(shù)據(jù)接口： I²C，串行
電壓電源： 模擬和數(shù)字
電源電壓： 4.4 V ~ 5.5 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
AD7294
Data Sheet
Rev. H | Page 30 of 48
DACA,DACB, DACC, DACD, REGISTERS (0x01 TO 0x04)
Writing to these register addresses sets the DACA, DACB, DACC,
and DACD output voltage codes, respectively. Bits[D11:D0] in
the write result register are the data bits sent to DACA. Bit D15
to Bit D12 are ignored.
Table 17. DAC Register (First Write)1
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
X
B11
B10
B9
B8
1 X is don’t care.
Table 18. DAC Register (Second Write)
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
ALERT STATUS REGISTER A (0x05), REGISTER B
(0x06), AND REGISTER C (0x07)
The alert status registers (A, B, and C) are 8-bit read/write
registers that provide information on an alert event. If a
conversion results in activating the ALERT/BUSY pin or the
alert_flag bit in the result register or TSENSE registers, the alert
status register can be read to gain further information. To clear
the full content of any one of the alert registers, write a code of
FF (all ones) to the relevant registers. Alternatively, the user can
write to the respective alert bit in the selected alert register to
clear the alert associated with that bit. The entire contents of all
the alert status registers can be cleared by writing a 1 to Bit D1
and Bit D2 in the configuration register, as shown in Table 24.
However, this operation then enables the ALERT/BUSY pin for
subsequent conversions. See the Alerts and Limits Theory
section for more details.
CHANNEL SEQUENCE REGISTER (0x08)
The channel sequence register is an 8-bit read/write register that
allows the user to sequence the ADC conversions to be per-
formed in autocycle mode. Table 22 shows the content of the
channel sequence register. See the Modes of Operation section
for more information.
Table 19. Alert Status Register A
Alert Bit
D7
D6
D5
D4
D3
D2
D1
D0
Function
V
IN3
high alert
V
IN3
low alert
V
IN2
high alert
V
IN2
low alert
V
IN1
high alert
V
IN1
low alert
V
IN0
high alert
V
IN0
low alert
Table 20. Alert Status Register B
Alert Bit
D7
D6
D5
D4
D3
D2
D1
D0
Function
Reserved
I
SENSE2
overrange
I
SENSE1
overrange
I
SENSE2
high alert
I
SENSE2
low alert
I
SENSE1
high alert
I
SENSE1
low alert
Table 21. Alert Status Register C
Alert Bit
D7
D6
D5
D4
D3
D2
D1
D0
Function
Open-diode
flag
Overtemp
alert
T
SENSEINT
high alert
T
SENSEINT
low alert
T
SENSE2
high alert
T
SENSE2
low alert
T
SENSE1
high alert
T
SENSE1
low alert
Table 22. Channel Sequence Register
Channel Bit
D7
D6
D5
D4
D3
D2
D1
D0
Function
Reserved
I
SENSE2
I
SENSE1
V
IN3
V
IN2
V
IN1
V
IN0
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