Data Sheet
AD7294
Rev. H | Page 9 of 48
TIMING CHARACTERISTICS
I2C Serial Interface
AVDD = DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V, VREF = 2.5 V internal or external; VDRIVE = 2.7 V to 5.5 V; VPP = AVDD to 59.4 V;
DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; TA =
40°C to +105°C, unless otherwise noted.
Table 4.
Limit at T
MIN, TMAX
Unit
Description
f
SCL
400
kHz max
SCL clock frequency
t
1
2.5
s min
SCL cycle time
t
2
0.6
s min
t
HIGH, SCL high time
t
3
1.3
s min
t
LOW, SCL low time
t
4
0.6
s min
t
HD,STA, start/repeated start condition hold time
t
5
100
ns min
t
SU,DAT, data setup time
t
6
0.9
s max
t
HD,DAT, data hold time
0
s min
t
HD,DAT, data hold time
t
7
0.6
s min
t
SU,STA, setup time for repeated start
t
8
0.6
s min
t
SU,STO, stop condition setup time
t
9
1.3
s min
t
BUF, bus free time between a stop and a start condition
t
10
300
ns max
t
R, rise time of SCL and SDA when receiving
0
ns min
t
R, rise time of SCL and SDA when receiving (CMOS compatible)
t
11
300
ns max
t
F, fall time of SDA when transmitting
0
ns min
t
F, fall time of SDA when receiving (CMOS compatible)
300
ns max
t
F, fall time of SCL and SDA when receiving
20 + 0.1C
ns min
t
F, fall time of SCL and SDA when transmitting
C
b
400
pF max
Capacitive load for each bus line
2 C
b is the total capacitance in pF of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.
Timing and Circuit Diagrams
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t9
t3
t1
t11
t4
t10
t4
t5
t7
t6
t8
t2
SDA
SCL
05747-
002
Figure 2. I2C-Compatible Serial Interface Timing Diagram
CL
50pF
TO OUTPUT PIN
VOH (MIN) OR
VOL (MAX)
200A
IOL
IOH
05747-
003
Figure 3. Load Circuit for Digital Output