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參數(shù)資料
| 型號： | 28F160C18 |
| 廠商： | Intel Corp. |
| 英文描述： | 1.8V Advanced+ Boot Block Flash Memory(1.8V高級引導(dǎo)塊閃速存儲器) |
| 中文描述： | 1.8高級啟動塊閃存（1.8V的高級引導(dǎo)塊閃速存儲器） |
| 文件頁數(shù)： | 9/52頁 |
| 文件大?。?/td> | 272K |
| 代理商： | 28F160C18 |
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E
28F160C18
9
ADVANCE INFORMATION
Table 2. 1.8 Volt Advanced+ Boot Block Pin Descriptions
(Continued)
Symbol
Type
Name and Function
V
PP
INPUT/
SUPPLY
PROGRAM/ERASE POWER SUPPLY:
[0.9 V
–1.95 V or 11.4 V–12.6 V]
Operates as a input at logic levels to control complete device protection.
Supplies power for accelerated program and erase operations in 12 V
±
5% range. This pin cannot be left floating.
Lower
V
PP
≤
V
PPLK
, to protect all contents
against Program and
Erase commands.
Set V
PP
= V
CC
for in-system read, program and erase operations
. In
this configuration, V
PP
can drop as low as 0.9 V to allow for resistor or
diode drop from the system supply. Note that if V
PP
is driven by a logic
signal, V
IH =
0.9 V. That is, V
PP
must remain above 0.9 V to perform in-
system flash modifications.
Raise V
PP
to 12
V
±
5% for faster program and erase
in a production
environment. Applying 12 V
±
5% to V
PP
can only be done for a
maximum of 1000 cycles on the main blocks and 2500 cycles on the
parameter blocks.
V
PP
may be connected to 12 V for a total of 80 hours
maximum. See Section 3.4 for details on V
PP
voltage configurations.
V
SSQ
/
GND
SUPPLY
I/O GROUND / DEVICE GROUND:
For all internal circuitry. All ground
inputs
must
be connected.
NC
NO CONNECT:
Pin may be driven or left floating.
2.2
Block Organization
The 1.8 Volt Advanced+ Boot Block is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash
device.
Each
block
independently of the others up to 100,000 times.
For the address locations of each block, see the
memory maps in Appendix E.
can
be
erased
2.2.1
PARAMETER BLOCKS
The 1.8 Volt Advanced+ Boot Block flash memory
architecture includes parameter blocks to facilitate
storage of frequently updated small parameters
(i.e., data that would normally be stored in an
EEPROM). Each device contains eight parameter
blocks of 4-Kwords.
2.2.2
MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into equal size 32-Kword
main blocks for data or code storage. The 16-Mbit
contains 31 main blocks.
3.0
PRINCIPLES OF OPERATION
The 1.8 Volt Advanced+ Boot Block flash memory
architecture
utilizes
a
algorithms
to
simplify
operations. The CUI allows for 100% CMOS
-
level
control inputs and fixed power supplies during
erasure and programming.
CUI
program
and
automated
and
erase
The internal WSM completely automates program
and erase operations while the CUI signals the start
of an operation and the status register reports
status. The CUI handles the WE# interface to the
data and address latches, as well as system status
requests during WSM operation.
3.1
Bus Operation
The 1.8 Volt Advanced+ Boot Block flash memory
devices read, program and erase in
-
system via the
local CPU or microcontroller. All bus cycles to or
from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate
the data flow in and out of the flash component:
CE#, OE#, WE# and RST#. These bus operations
are summarized in Table 3.
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