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參數(shù)資料
| 型號(hào)： | 28F160C18 |
| 廠商： | Intel Corp. |
| 英文描述： | 1.8V Advanced+ Boot Block Flash Memory(1.8V高級(jí)引導(dǎo)塊閃速存儲(chǔ)器) |
| 中文描述： | 1.8高級(jí)啟動(dòng)塊閃存（1.8V的高級(jí)引導(dǎo)塊閃速存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 14/52頁(yè) |
| 文件大小： | 272K |
| 代理商： | 28F160C18 |
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28F160C18
E
14
ADVANCE INFORMATION
block in memory. Once the erase sequence is
started, writing the Erase Suspend command to the
CUI
suspends
the
erase
predetermined point in the erase algorithm. The
device continues to output status register data after
the Erase Suspend command is written. Polling
status register bits SR.6 and SR.7 will determine
when the erase operation has been suspended
(both will be set to
“1”). t
WHRH2
/t
EHRH2
specify the
program suspend latency.
sequence
at
a
A Read Array/Program command can now be
written to the CUI to read/program data from/to
blocks other than that which is suspended. This
nested Program command can subsequently be
suspended to read yet another location. The only
other valid commands while erase is suspended are
Read Status Register, Read Configuration, Read
Query, Program Setup, Program Resume, Erase
Resume, and Lock Setup. During erase suspend
mode, the chip can be placed in a pseudo
-
standby
mode by taking CE# to V
IH
. This reduces active
current consumption.
Issuing the Erase Resume command continues the
erase sequence (when CE# = V
IL
) and status
register bits SR.6 and SR.7 will automatically be
cleared. The device automatically outputs status
register data when read (see Figure 13 in Appendix
B,
Erase Suspend/Resume Flowchart
) after the
Erase Resume command is written. RST# must
also remain at V
IH
.
As with the end of a standard erase operation, the
status register must be read and cleared before the
next instruction is issued.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| 28F160F3B95 | 制造商:Intel 功能描述: |
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